Recent progress of oxide-TFT-based inverter technology

Oxide semiconductor-based thin-film transistor (oxide-TFT) technology have gained significant attention since the innovation of n-channel oxide-TFT using ZnO and amorphous In–Ga–Zn–O (a-IGZO) channels because of their superior device properties including excellent electrical property such as high TFT mobility over >10 cm2/Vs and the low-cost manufacturability originating from the low-temperature processability. Already, n-channel a-IGZO-TFT is widely employed as a TFT pixel switching backplane for several high-performance active-matrix flat-panel displays, and oxide-TFT technology to date is well acknowledged as the best TFT technology for future device applications in the wide range area of electronics such as sensors, Internet of things (IoT), energy-harvesting, medical/bio-interface device, etc. Therefore, the development of large-scale circuit beyond discrete TFT device level becomes increasingly important and is vital to advance the next stage of oxide-TFT technology. In particular, developing oxide-TFT-based inverter device technology is the key for developing several digital and analog circuits. In this paper, the recent progress and challenges in oxide-TFT-based inverter technology, including unipolar NMOS, PMOS, CMOS, and CMOS-like inverters using ambipolar oxide-TFT, are reviewed.


Introduction
Thin-film transistor (TFT) is the key technology for developing next-generation flexible/wearable electronics implemented on any low-cost substrates [1,2]. Among several TFT technologies including organic, amorphous Si, and low-temperature poly-Si (LTPS)-TFTs, oxide semiconductor-TFT (oxide-TFT) technology represented by amorphous-In-Ga-Zn-O (a-IGZO)-TFT is widely recognized as the most promising because the n-channel oxide-TFT meets the requirements for both the high device performance and high manufacturability for future electronics [3,4,5,6]. Since a-IGZO-TFT exhibiting excellent device characteristics such as high TFT mobility of > 10 cm 2 /Vs, low-off current as low as < 1 pA, low-voltage operation of ±3 V, steep subthreshold slope of ∼ 0.1 V/decade, etc. can be fabricated by conventional dc/rf/ac sputtering on a large-size glass substrate (for example, 2840 mm × 3370 mm (Gen 10+)) at the low-temperature process ( < 300 o C), the a-IGZO-TFT have been already commercialized as a TFT pixel switching backplane for several high-performance active-matrix flat-panel displays (AM-FPDs) such as lowpower consumption liquid crystal display (AMLCD) mobile display and high-resolution (3840 × 2160 (4K UHD))-PC monitor and high-resolution and large-size (4K-83 class) organic light-emitting diode (AMOLED) TV panels and so on [7,8]. Moreover, the high oncurrent capability originating from high TFT mobility in n-channel oxide-TFT enable a peripheral integration of gate driver circuits, which is composed of several types of logic inverter gates, with a pixel circuit for AM-FPDs [9]. The gate driver monolithic circuit (GDM) technology offers the compactness and mechanical reliability, and overall cost reduction by eliminating the external driver ICs and is critical for mobile display applications with narrow bezels.
For next-generation ubiquitous network society, moreover, flexible/wearable electronic devices become more increasing important and are highly required with the low-power operation, low-cost manufacturing process, and higher-level integrations of various functions including high-resolution display, high-density information storage, high-speed information processing/transfer, several sensors such as position-sensitive pressure sensors, temperature sensor, health sensing devices, etc., which is known as system-on-glass (SOG) and systemon-panel (SOP) technology [10][11][12][13].
Therefore, developing TFT-based inverter technology, which is a fundamental building block for digital logic gate circuits and several analog circuits in the current modern electronics, is critical for GDM and SOG technology [14]. However, traditional silicon semiconductors device technology cannot meet the requirements to develop such fundamental devices onto a wide variety of large size and soft substrates such as plastic, paper, and fabric. Developing oxide-TFT-based inverter and the related logic gate are indispensable for highperformance, cost-effective future ubiquitous devices [15][16][17].
Hence, this paper reviews the recent progress and challenges in oxide-TFT-based inverter technology developments. The oxide-TFT-based inverters such as (1) unipolar n-type metal-oxide-semiconductor (NMOS), (2) p-type MOS (PMOS), (3) complementary metaloxide-semiconductor (CMOS) inverters including (1) p-organic/n-oxide-TFT hybrid CMOS and (2) all-oxide-TFT-based CMOS are discussed with the recent progress of p-channel oxide-TFT development. (4) CMOS-like inverter using two identical ambipolar-TFT using (1) bi-layered channel structure composed of organic/oxide semiconductors and (2) Tin monoxide (SnO) channel are also discussed. Finally, we briefly reviewed ring oscillator (RO) circuit development using oxide-TFT inverters for large-scale circuit applications.

Oxide-TFT-based NMOS inverter
So far, numerous efforts have been demonstrated for developing oxide-TFT-based inverters and the related circuit applications such as flip-flop, RO, shift register, logic gates (NAND and NOR gate), radio-frequency identification (RFID) tag, etc. Due to the absence of highperformance p-channel oxide-TFTs originating from the intrinsic electronic structure nature, in which the valence band maximum (VBM) is composed of a localized Oxygen 2p orbital [3,18], the most reported oxide-TFT inverter is currently NMOS inverter implemented only by n-channel oxide-TFTs. Figure 1(a,b) shows the schematic of equivalent circuit diagrams for NMOS inverters with saturated enhancement (E)-mode and depletion (D)-mode TFTs as an active load (i.e. pull-up device) [19]. The enhancementtype inverter consists of two E-mode TFTs with positive threshold voltage (V th ) for both load and drive-TFT devices. The gate terminal connects to the drain terminal, also known as diode-connect or diode-load, for the load-TFT, which works as non-linear resistor, and always operates in the saturation regime (Figure 1(a)). When the input voltage (V IN ) is zero or low level, the drive-TFT is in the cut-off. Consequently, no steady-state current flows in the circuit, and the load-TFT pulls the output up toward the power supply (V dd ). The enhancementload-type NMOS inverter can be fabricated by a simple fabrication process but cannot be operated with rail-torail signal swing due to the limitation of high output voltage (V OH ), which is determined by V dd -V th . On the other hand, depletion-load-type inverter is constructed using D-mode TFT with negative V th as a load device, in which the gate and source terminals are tied, also called as 'zero-V GS ' (Figure 1 (b)). In this case, the Dmode load-TFT is always 'ON' because of the gate bias (V gs (load)) = 0 V regardless of the V IN . The depletionload inverter exhibits better inverter characteristics such as sharp inverter transition, large noise margin, lowpower consumption, and smaller overall layout area than the enhancement-load-type device. Figure 1(c) also illustrates the typical voltage transfer characteristics (VTC) of an inverter. At V IN = 0 V, the output voltage (V OUT ) is close to V dd . As V IN increases and the drive-TFT turns on, V OUT reaches to zero beyond the inverter threshold voltage (V T ), which is defined by V dd /2, due to steady-state current flow. The VTC provides the important fundamental device parameters such as V T , voltage gain, noise margin (NM), power dissipation (P), and so on. The voltage gain, which is defined as dV OUT /dV IN , is often used as a benchmark to indicate the device quality of TFT-based inverters, especially oxide-TFT-based inverter. Noise margins at high and low levels (NM H and NM L ) and transition width ( V IN ) are also defined by NM H = V OH -V IH , NM L = V IL -V OL and V IN = V IH -V IL , where V IH , V IL , V OH , and V OL are input and output voltages at high and low levels, respectively. In addition to the TFT device performances, the VTC is largely affected by TFT device parameters such as the V th of drive/load-TFTs and the drive-to-load ratio (k R ), defining k R = (W/L) drive/(W/L) load-TFTs. Here, the W and L are the channel width and length of the drive and the load-TFTs. In general, TFT should be designed with small k R to achieve good VTC such as high voltage gain and large NM. Figure 2 shows the n-channel oxide materials and the progress of output voltage gain of the reported oxide-TFT-based NMOS-inverters. Table 1 also summarizes the details of device structure parameters and device performances of the reported oxide-TFT-NMOS inverters including enhancement and depletion-load types. Since several good n-type oxide semiconductor materials are currently available for n-channel oxide-TFT, the reports regarding NMOS inverter over 30 papers are easily found. The major n-channel oxide material is a-IGZO (several composition ratios of In:Ga:Zn are available for a-IGZO) and ZnO. Since the first report of oxide-NMOS inverter   [20], the gain is significantly improving last decade, and the maximum gain currently reaches > 380 for ZnO-TFT inverter with depletion-load-type inverter [21]. Since the depletion-load-type inverter is highly preferable in terms of device performances, most of the reported device is depletion-load-type inverter.
Remarkable progress on the device performances of oxide-NMOS inverter can be seen in ZnO-TFT-based-NMOS inverters with the voltage gain of 248 [37] and a-IGZO-TFT-NMOS inverter with 220 [39], respectively. Lee et al. developed a Schottky-barrier a-IGZO-TFT operating in the deep subthreshold regime by using the high-resistive a-IGZO channel and Mo electrode. The depletion-load-type NMOS inverter exhibited good VTC performances such as high voltage gain > 220 (V dd = 2V) and low output-power consumption of < 150 pW, which demonstrated a high potential of oxide-NMOS inverter for a low-power device that can be driven by a nanowatt power source. In 2017, Alshammari et al. [21] achieved a high voltage gain of 382 (V dd = 25 V) in a depletion-loadtype NMOS inverter using ALD-fabricated ZnO-TFTs. They concluded the high-performance inverter were originated from the excellent ZnO-TFT characteristics such as high TFT mobility of ∼ 15 cm 2 /Vs and small s-value of ∼ 130 mV/dec by using high-k HfO 2 gate oxide and SnO 2 gate electrodes. Moreover, the low propagation delay of 150 ns/stage and high operation frequency of 303 kHz was also demonstrated in the RO circuit using the ZnO-TFT-based depletion-type NMOS inverter.
For the depletion-load NMOS inverter, fabricating two stable E-mode and D-mode oxide-TFTs on a single chip, is required. In general, two E-mode devices are firstly fabricated on a substrate, and then one device converts to D-mode TFT by extra post-process steps. Since the donor density in the n-channel is a dominant Table 1. Summary of the device structure parameters and device performances for the reported oxide-TFT-based-NMOS inverters. The W and L are the channel width and length of load/drive-TFTs, respectively.  factor for determining the V th in oxide-TFT, increasing the donor density is required for fabricating Dmode TFT. It is well known that oxygen deficiency and impurity hydrogen work as an electron donor in many n-type oxides [52,53]. Thus, the primal technique is the controlling of such defects and impurity levels. The oxygen deficiency can be easily controlled by the channel fabrication process conditions such as oxygen partial pressure during deposition/postannealing process, but these conventional techniques are difficult to selectively fabricate D-mode TFT next to E-mode device. To electively fabricate D-mode TFTs, several approaches have been proposed, including the control of channel compositions [31,35], the channel layer thickness control [25], local laser annealing [34], the use of different gate electrode materials, the formation of capping layer [33,40], low-k/high-k double gate oxide, top-gated structure, dual-gated structure [32] etc. Moreover, the fabrication of D-mode TFT by utilizing device degradation processes such as bias stress [30], light-irradiation [47], etc. was also proposed.
Several circuit-level demonstrations by using solution printing/inkjet-processed oxide-TFTs have been also reported. Recently, Shao et al. [51] developed 64 × 64 TFT array on glass substrate using In 2 O 3 /IGZO-bilayer TFTs (Mobility ∼ 18.80 / 28.44 cm 2 /Vs) fabricated by a self-confined inkjet printing technology and demonstrated good inverter characteristics with a voltage gain of 112.

Oxide-TFT-based PMOS inverter
PMOS inverter is composed of p-channel-TFTs for drive and load-TFT devices. Since n-channel device usually shows higher carrier mobility, NMOS inverter exhibits several advantages such as higher density, and higher speed operations. Therefore, NMOS inverter is generally preferable in most circuit applications, but the advantages of PMOS inverter for some specific applications can be found. As an example, LTPS-TFT-based PMOS inverter have been proposed for reducing the manufacturing cost and improving the yield of LTPS-TFT for largesized AM-FPDs [54]. Instead of the CMOS driver circuit, the fabrication process can be also simplified, and the cost can be reduced by using unipolar p-channel TFT technology. Since n-type LTPS-TFTs show poor stability due to hot carrier stress degradation; moreover, PMOS inverter are expected greatly to develop more stable circuits than LTPS-CMOS circuits. It is also well known that several good p-channel-TFTs are available in inkjet/printable-organic semiconductors [55,56]. Owing to the high potential of the cost-effective manufacturing process for flexible display and microelectronics, many organic-TFT-based PMOS inverter have been demonstrated. In contrast, only one demonstration for both enhancement/depletion-load-type PMOS inverter using SnO-TFTs (Mobility of ∼ 1.6 cm 2 /Vs, V th = −0.3 V and the on/off current ratio of 10 3 -10 4 ) can be found in oxide-TFT technology [57]. Oxide-TFT-based PMOS inverter is largely behind form NMOS inverter due to a low number of device quality p-type oxides.

Oxide-TFT-based CMOS inverter
Although unipolar NMOS and PMOS inverters can be fabricated by relatively simple fabrication process with a less number of process steps, Complementary metal-oxide -semiconductor (CMOS) inverter technology, configured by both n-channel and p-channel-TFTs, are highly demanded because CMOS device exhibits significant advantages for most digital and analog circuit applications owing to the better device performances such as low noise immunity, low-power consumption, low heat dissipation, small device footprint area, etc. These features allow the development of more simple circuit architectures with high packing density on integration circuit applications. Therefore, TFT-based CMOS is a critical technology for SOP, which requires to highly integration of various functional devices with display. Figure 3(a) shows the equivalent circuit diagram of the CMOS inverter with p-channel and n-channel-TFTs as pull-up and pull-down devices, respectively. In CMOS, both the input gate and output (i.e. drain) terminals are tied together, and the source terminal in n-channel and p-channel-TFT connect to a ground and supply voltage (i.e.V dd ), respectively. p-channel and n-channel TFTs operate complimentary in drive and load-devices by the input signals. When the V IN is low, n-channel-TFT is 'off', while p-channel TFT stays 'on'. Thus, pchannel-TFT pulls the output up toward the V dd , and the V OUT appears at high. When the V IN moves toward high, n-channel-TFT turns on at the V IN > V th (n), the V OUT transits to low state. Figure 3(b) also illustrates the cross-sectional view of a typical CMOS inverter consisting of inverted staggered-type, i.e. bottom-gate and top-contact structure, n-channel and p-channel-TFTs on a substrate. The bottom-gate structure is the most common for oxide-TFTs because the top-gate fabrication process often causes the generation of extra defects in the channel layer and serious degradations of TFT device performances.

Oxide/organic-TFT-based hybrid CMOS inverter
As already explained, currently good oxide-TFT are almost n-channel, while good organic-TFT vice versa. Thus, these materials do not have adequate complementary counterparts to each other. To address this, a hybrid-CMOS inverter comprised of n-channel oxide-TFT and p-channel organic-TFT has been proposed. Figure 4 shows these channel materials and the progress of output voltage gain of hybrid-CMOS-inverters using n-oxide/porganic-TFT. Table 2 also lists the details of device performances of the reported hybrid-CMOS inverters.
Several TFT material combinations for oxide/organic-TFT-hybrid-CMOS have been reported so far. In the early stage, the major combination was n-ZnO and n-a-IGZO with p-pentacene, which is known as an organic semiconductor with a relatively high hole mobility of ∼ 1 cm 2 /Vs, and the high voltage gain of ∼ 100 was achieved by using these oxide and organic-TFTs and proper device dimensional design. The current popular hybrid structure is composed of n-a-IGZO and p-carbon nanotube (CNT)-TFTs with high hole mobility.
In  [61]. Poly (9,9-dioctylfluorene-alt-bithiophene) (F8T2), which is also a well-known inkjet printable-organic semiconductor having a hole mobility of ∼ 0.1 cm 2 /Vs and good stability against environmental oxygen and residual impurities, is also widely used for the counterpart of n-channel oxide-TFTs in the oxide/organic-TFT-based hybrid-CMOS inverter [62].  By taking the advantages of low-temperature processability and printing/inkjet process compatibility for both oxide and organic-TFT technologies, three-dimensional (3D) CMOS structure, which enable to develop the highly integrated device, have been also proposed. Figure 5 shows 3D-vertically stacked flexible hybrid-CMOS inverters that made up of n-a-IGZO and p-F8T2-TFTs, where all the fabrication processes were performed at temperatures < 120°C on plastics. Since the n-a-IGZO-TFT (Mobility of ∼ 3.2 cm 2 /Vs) and p-F8T2-TFTs ( ∼ 1.7×10 −3 cm 2 /Vs) are constructed by inverted-staggered and top-gate structure, respectively, the gate terminals are shared in these TFTs. ( Figure  5(b)). The maximum voltage gain is ∼ 67, and the NM H and NM L were ∼ 10.4 and ∼ 18.3V (V dd = 30V), showing that the inverter guarantees a large allowance for logic operation ( > 20% of V dd ). Moreover, the flexible NAND logic circuit was also demonstrated by using the 3D-stacked hybrid-CMOS inverter [69].
Owing to excellent material properties such as high carrier mobility, high current density capability, excellent mechanical flexibility/stretchability, and good process compatibility with low-cost solution processes of CNT, p-cannel CNT-TFT is the highly promising counterpart for the n-channel oxide-TFT for oxide/organic hybrid-CMOS inverter. Already, several n-oxide-TFT/p-   ∼ 10 6 ) [89]. The achievement is considered mainly by originating from the use of high-performance of pchannel TFT and the well-balanced electrical performances of CNT-TFTs and a-IGZO-TFTs.

All-oxide-TFT-based CMOS inverter
Intensive research for all-oxide-TFT-based CMOS inverter, which is composed of both n-channel and p-channel oxide-TFTs, is currently ongoing. However, due to the absence of oxide semiconductors that can control p/n polarity at device-quality level, a single oxide material-based CMOS has not been developed yet. Therefore, all the current oxide-CMOS is constructed by different channel materials for n and p-channel oxide-TFTs. Figure 6(a) shows the channel materials of p and n-channel oxide-TFTs for all-oxide-TFT CMOS inverters. Several material choices are available for nchannel oxide-TFTs, including ZnO, a-IGZO, SnO 2 , In 2 O 3, etc. In contrast, only material, SnO, Cu 2 O and NiO channels, which intrinsically exhibit p-type nature, are available for p-channel oxide-TFT, although several p-type oxides have been discovered so far [91][92][93]. The current main combination is n-a-IGZO and p-SnO-TFTs, which mainly comes from relatively better TFT device performance of SnO-TFT than other p-channel oxide-TFT, in addition to the low-temperature device processability as low as 300°C [94]. Figure 6(b) also shows the progress of voltage gain in the reported all-oxide-TFT-based CMOS inverters. Table 3 summarizes the details of device structure parameters and device performances for the reported alloxide-CMOS inverters. Since the first demonstration of oxide-TFT-based CMOS inverter using n-In 2 O 3 (Mobility of ∼ 0.054 cm 2 /Vs and V th ∼ 10 V) and p-SnO x (0.0047 cm 2 /Vs and ∼ 30 V) with the voltage gain of 11 [95], several efforts to improving inverter performances accompanied by p-channel oxide-TFT development have been intensively devoted.    [116].
The recent progress of all-oxide-CMOS inverter is remarkable, but the device performances are still not satisfactory yet. This is mainly due to the unbalanced device performances of n and p-channel oxide-TFTs and is attributed to the poor TFT performance of p-channel oxide-TFTs. The main reason for the poor device performances for p-channel-TFTs is due to the presence of high-density subgap defects including bulk channel and front-interface/back-channel surfaces. Therefore, several attempts to eliminate subgap defects for p-channel oxide materials have been made. For p-SnO channels, oxygen vacancy (Vo) that forms hole trap above the VBM is the root causes for degrading the TFT performances [113,117,118]. Post-thermal annealing is widely used not only to crystallize p-type oxide channels but also to reduce carrier trap states. However, the annealing condition for p-channel oxides is quite limited due to the existence of undesired oxide with higher valence state of metal cations, e.g. Sn(IV)O 2 in Tin oxide [119,120]. So far, several approaches including hydrogen annealing, passivation formation, hightemperature deposition have been proposed to reduce subgap defects for SnO. Although the TFT device has not been demonstrated yet, epitaxial SnO films with remarkable high Hall mobility of ∼ 10 cm 2 /Vs with a low hole density of ∼ 10 16 cm −3 have been successfully grown by high-temperature PLD deposition [121]. The achievement brings high expectations to furthermore improve TFT characteristics in the p-channel SnO-TFTs.
On the other hand, V o is also energetically stable point defect but electrically inactive defect for Cu 2 O channel [122,123]. Therefore, amphoteric Cu interstitial defect (Cu i ) is considered to have a large responsibility for the poor device performance of Cu 2 O-TFT [115,124].
Although the Cu 2 O has high hole mobility, moreover, the TFT mobility is quite low. Recent studies clarified that the back-channel defect degraded the TFT performances and found eliminating back-channel Cu i was the key to improve the device performances. Figure 7(a) shows the improvement of TFT performances of Cu 2 O-TFT by back-channel defect termination by using sulfur ion generated from Thiourea solution. By reducing the back-channel Cu i defect originating from the formation of CuSO 4 back-channel layer (Figure 7(b)), significant improvements of the off-current down to as low as ∼ 1 pA and s-value are observed. The simple back-channel defect termination using Thiourea solution offers the improved Cu 2 O-TFTs exhibiting the mobility of ∼ 1.81 cm 2 /Vs, s-values of ∼ 1.3 V/dec., and the on/off current ratio of ∼ 6.0 × 10 6 .1 [115]. Min et al. [111] also demonstrated the improvement of Cu 2 O-TFT performances by forming CuO back-channel layer and obtained field-effect mobility of ∼ 0.75 cm 2 /Vs, svalues of ∼ 0.11 V/decade, and the on/off current ratio of ∼ 2.81 × 10 8 . Figure 7(c,d) also shows the VTC and the output voltage gains for oxide-CMOS inverter using the backchannel defect terminated p-channel Cu 2 O-TFT with nchannel a-IGZO-TFTs. The inverters exhibited a sharp and full signal switching with rail-to-rail output swings, and the maximum gain of 232 (V dd = 70 V) ( Figure  7 (d)). The improvement of the inverter characteristics was attrubuted to the improved device performances of p-Cu 2 O-TFT by back-channel defect termination, especially, the improvements of the s-value and the offcurrent. Therefore, improving the device performance  of p-channel oxide-TFT is essential to develop highperformance all-oxide-TFT-based CMOS technology.

Ambipolar oxide-TFT-based CMOS-like inverter
Besides these oxide-TFT inverters above, the development progress of oxide-TFT-based CMOS inverter can be also confirmed in CMOS-like inverter using two identical ambipolar-TFTs, in which both electron and hole contribute the carrier conductions [125]. Therefore, ambipolar CMOS-like inverter is only one device that can be fabricated by a single material in the current oxide-TFT technology because there is no oxide semiconductor that can control the carrier types in electronic device quality level. The type of device is expected greatly to develop extremely cost-effective simple fabrication steps without any additional process steps such as the channel polarity control, the adjustment of Vth of TFTs, and advanced patterning of p and n-channel-TFTs in separate regions. The process advantages also offer the development of high-density integrated device architectures for both planar and vertical geometric configurations. In addition, the unique electrical behavior operated in both the first and third quadrants is also promising to reduce complexity of circuit design and to develop novel logic circuits. Therefore, ambipolar-based-CMOS-like inverter has received much attention in these recent years [126,127]. Figure 8 shows the equivalent circuit diagram for CMOS-like inverter and the schematic of the corresponding carrier flows before and after the output voltage inversion for the first (right) and third quadrants (left), which correspond to positive and negative inputs, respectively. The device can operate in both the positive and negative inputs and exhibits inverter actions in both the first and third quadrant regions by transiting p-and nchannel modes in both the TFTs. At 0 < V IN < V T for the first quadrant, the pull-up-TFT works as p-channel mode and only holes contribute to the current flow. While the pull-down-TFT operates in n-channel mode and is 'off', but exhibits hole current flow. Therefore, the V OUT cannot fully swing to the supply voltage. At V IN = V dd /2, i.e. inverter threshold, only electrons and holes contribute the current in n-channel and p-channel modes, respectively. At V IN > V T , both devices behave as a unipolar device with only electrons contributing to the current flow, and the V OUT also cannot reach 0 V. Therefore, the VTC for ambipolar CMOS-like inverter shows a unique 'Z-shape'.
Several organic ambipolar-TFTs such as CNT, graphene, several organic semiconductor channels, have been fabricated. Since many oxide semiconductors have a wide-bandgap over 3.0 eV due to the nature of strong ionicity of chemical bonding, ambipolar behavior have been only currently observed in SnO with a narrow bandgap of 0.7-0.8 eV [128]. Therefore, a bi-layered channel structure consisted of ntype oxide and p-type organic have been proposed for ambipolar-TFT, including n-channel such as a-IGZO, ZnO, In 2 O 3 with organic semiconductor channels. Note that the inverter is constructed by two identical single TFT with ambipolar channel using a bi-layered structure of n-oxide/p-organic semiconductors and distinguished from hybrid CMOS-inverter composed of p-channel organic-TFT and n-channel oxide-TFT as discussed in Section 4.1. Table 4 summarizes the details of device structure parameters and device performances for the reported CMOS-like inverter using ambipolar-TFT with oxide/ organic-bi-layered channel. Liu et al. fabricated an ambipolar-TFTs with bi-layered channel made up of vertically stacked n-a-IGZO and p-pentacene and attained a high voltage gain as high as 60 in both the first and third quadrants of VTCs [129]. The ambipolar-TFT exhibited good performances such as electron mobility of 23.8 cm 2 /Vs and hole mobility of 0.15 cm 2 /Vs, respectively. Kim et al. [130] also fabricated ambipolar-TFT using bi-layered channel comprised of single-walled carbon nanotubes (SWCNTs) and amorphous Zinc-Tin oxide (ZTO) and demonstrated well-balanced electron and hole transport exhibiting electron mobility of 11.5 cm 2 /Vs and hole mobility of 4.2 cm 2 /Vs. The ambipolar-TFT-based CMOS-like inverter exhibited a gain of > 20. Recently, high voltage gain of 88 and 124 for the first and third quadrants in the VTC were achieved in ambipolar-TFT with bi-layered structured channel of a-IGZO/C8-BTBT, which is semiconducting polymer with dioctylbenzothieno [2,3-b]benzothiophene [131]. Figure 9 summarizes the TFT operation modes for the reported SnO-TFTs. Although the most reported SnO device is p-channel TFT, two types of operation modes, i.e. p-channel and ambipolar modes, are identified in the reported SnO-TFTs. A recent study clarified the origin of the different operation modes in the reported SnO-TFTs, and back-channel surface defect density had a large responsibility of the TFT operation mode [138]. Figure  10(a) shows the variation of the transfer characteristics of SnO-TFTs with different back-channel defect density, which controlled by surface wet-etching with diluted Tetramethylammonium hydroxide (TMAH) and ALD-Al 2 O 3 passivation. The corresponding output characteristics are also shown in Figure 10(b). The pristine-TFTs without back-channel treatment show weak ambipolarity. Since the back-channel wet-etching induces extra back-channel defect over ∼ 10 14 /cm 2 eV, the extra defect completely removes n-channel mode and produces Table 4. Summary of the device parameters and device performances for the reported CMOS-like inverter using hybrid ambipolar-TFT composed of bi-layered of n-channel oxide and p-channel organic.  p-channel SnO-TFTs. Therefore, the absence of ambipolarity in the reported p-channel SnO-TFTs is due to the presence of high-density back-channels defect. In contrast, the ALD-Al 2 O 3 back-channel passivation improves n-channel transport, and makes the device exhibiting good symmetric ambipolar behavior. This is originated from the back-channel defect termination that can reduce to ∼ 10 13 cm −2 eV −1 . Table 5 summarizes the development progress of CMOS-like inverter using ambipolar SnO-TFTs. The obtained voltage gain of the first ambipolar SnO-TFTbased CMOS-like inverters was only ∼ 2.7 due to the unbalanced device performances for n-and p-channel modes [139]; specifically, the low mobility of n-channel mode. Significant improvement of the VTC by achieving the balanced performances of n-and p-channel mode was made by device passivation and remarkably high gain of 100 was attained by Luo et al. [140]. Figure 10

Ring oscillator circuit using oxide-TFT inverters
Numerous demonstrations have been made in oxide-TFT and several inverter circuits such as flip-flop, ring oscillator (RO), shift register, logic gates (NAND and NOR gate), etc. These circuit-level demonstrations are also recognized as a benchmark for device quality of oxide-TFT and inverter. RO, which is constructed by odd numbers of inverting stage connected in series with the output feedback to the input, are fundamental building blocks used for clock oscillators, phase-locked loops, carrier frequency generator in a wide area of device applications such as computers and wireless communication devices. It is also widely used as a fundamental circuit for evaluating the intrinsic speed of inverter logic process. Table 6 summarizes the device performances of RO circuits using several types of oxide-TFT-based inverters. Several high-performance ROs using ZnO-TFT-based NMOS inverter were reported. Sun et al. fabricated 7stage RO with high operation frequency of > 1 MHz with signal propagation delay < 75 nsec/stage (V dd = 32 V) by using ZnO-TFT (Mobility > 15 cm 2 /Vs, V th ∼ 14 V, s-value 0.5 V/dec., and on/off current ratio > 10 8 ) [145].
The oscillation frequency (f ) is inversely proportional to the number of stages (n), is strongly affected by the propagation delay (t) in each stage. Therefore, the f is giving by f = 1/2t n . Since the t directly links to the device performances of TFT elements, improving the TFT performances is significant for RO characteristics. Several approaches to improving the dynamic characteristics of TFT have been proposed. Fabricating short-channel devices to increase channel conductance is a primary strategy to improve the TFT operation speed. Zhao et al. developed the 1 μm-channel-length ZnO-TFT with the mobility of ∼ 20 cm 2 /Vs, V th of ∼ 2 V, s-value of   [151] Another effective way is reducing the parasitic capacitance, which largely affects the operation speed due to the effect of charging/discharging, to improve the RO performances. Since the overlapping of gate and source/drain electrodes is often the main source of parasitic capacitance, in general, a self-aligned coplanar TFT structure is promising to reduce parasitic capacitance. Rahaman et al. improved the gate/SD offset regions by fluorine doping in the coplanar-structure a-IGZO-TFTs (W/L = 12 /4 and 96/4 for load and drive-TFTs) and demonstrated 23-stages RO with a high f of 2.27 MHz (V dd = 20 V) with a small t of 9.5 ns/stage [172]. Table 6. The summary of device structure parameter and device performance for ring oscillator circuits using several type of oxide-TFT inverters.
The RO circuits using a hybrid-CMOS inverter with p-pentacene/n-ZnO-TFTs and p-CNT/n-a-IGZO-TFTs were also demonstrated. The 5-stage ROs using p-CNT/n-a-IGZO-TFT hybrid-CMOS achieved good performances such as high f of 714 kHz and small t of 140 ns/stage [163]. Chen et al. also fabricated hybrid CMOS inverter composed of p-CNT (mobility of 8-15 cm 2 /Vs, and on/off current ratio of 10 5 -10 6 ) and n-a-IGZO (7-8 cm 2 /Vs, and 10 6 -10 7 ) and developed a largescale microelectronic circuit (41,000 TFTs for 501-stage RO circuit) on the flexible substrate. They also successfully demonstrated various logic gates (inverter, NAND, and NOR gates), RO (from 51 to 501 stages), and dynamic logic circuits (dynamic inverter, NAND, and NOR gates) [161].

Conclusions
A review for the current oxide-TFT-based inverter technology, including unipolar NMOS, PMOS, CMOS, and ambipolar-TFT-based-CMOS-like inverters, was presented. Remarkable progress was clearly seen in all the types of oxide-TFT-based inverters, especially NMOS inverter using a-IGZO-TFT and all-oxide-TFT CMOS inverter composed of p-SnO/n-a-IGZO-TFTs and p-Cu2O/n-a-IGZO-TFTs. Moreover, a large-scale logic circuits beyond discrete device level and the cost-effective inkjet/print-processed logic circuit were also developed, and the high potentials of oxide-TFT-based inverter for broad fields of next-generation electronics such as flexible, wearable, transparent, low-power, low-cost, etc. were clearly demonstrated.
The comparison of inverter performances of several types of oxide-TFT-based inverters was summarized in Table 7. Since excellent n-channel oxide-TFT is available, the oxide-NMOS inverter is the most advanced among these oxide-TFT inverter technologies and move forward to the next stages such as large-scale circuit and device reliability test. Even though the TFT performance of pchannel oxide-TFT is not satisfactory yet, oxide-CMOS inverter also exhibits solid advantages on device characteristics such as high voltage gain, better noise margin, and lower power dispersion. Relatively high voltage gain over 100 is also obtained in CMOS-like inverter using ambipolar-TFT, but it still requires a better understanding of ambipolar inverter operation and improve the fabrication process stability. PMOS inverter is largely behind other types. The presented review shows that oxide-TFT technology is surely progressing to the next development level, but still several issues that should be addressed to advance to the next level remain. For the oxide-TFT NMOS inverter, effective doping methods to precisely control the donor level for the adjustment of V th is highly demanded at the manufacturing levels. Since a rigid technology such as substitutional doping is not successful in a-IGZO channel yet, a furthermore understanding of material property including doping mechanism for oxide, particularly amorphous oxide, is vital, in addition to doping process development. Moreover, it clearly shows that the absence of high-performance pchannel oxide-TFTs hinders the high potential of oxide-TFT technology for a broad field of next-generation electronic device applications. The development of pchannel oxide-TFT that exhibits comparable device performances with n-channel oxide-TFTs is indispensable for high-performance all-oxide-TFT-based CMOS technology. Several significant innovations to improve the device performances have been made so far. However, it still highly requires significant breakthroughs at the levels of material and device-level developments for p-channel oxide-TFTs to realize high-level integrated circuits using oxide-TFTs.

Disclosure statement
No potential conflict of interest was reported by the author(s).

Notes on Contributor
Kenji Nomura received his PhD degree in Material science engineering from the Tokyo Institute of Technology (Tokyo Tech), Japan in 2004. He has been a professor at the Jacobs School of Engineering at the University of California, San Diego since 2018.

Data availability statement
Data available on request from the authors.