Low-temperature activation under 150°C for amorphous IGZO TFTs using voltage bias

ABSTRACT Proposed herein is a new technique of activation for the backplane of low-temperature amorphous indium gallium zinc oxide thin-film transistors (a-IGZO TFTs) by applying a bias voltage to gate, source, and drain electrodes and simultaneously annealing them at 150°C. This ‘voltage bias activation’ can be an effective method of reducing the backplane processing temperature from 300°C to 150°C. Compared with the reference a-IGZO TFTs fabricated at 300°C, the a-IGZO TFTs fabricated through voltage bias activation showed sufficient switching characteristics: 10.39 cm2/Vs field effect mobility, 0.41 V/decade subthreshold swing, and 3.65 × 107 on/off ratio. These results were analyzed thermodynamically using infrared micro-thermography. In the case of the positive gate voltage bias condition, the maximum temperature of the a-IGZO channel increased to 48°C, and this additional annealing effect and activation energy lowering compensated for the insufficient thermal energy of annealing at a low temperature (150°C). With this approach, a-IGZO TFTs were successfully fabricated at a low temperature.


Introduction
Amorphous indium gallium zinc oxide thin-film transistors (a-IGZO TFTs) have gained international attention for the backplane technologies of the next-generation flexible displays since Hosono et al. first published a paper about 'In-Ga-Zn-O TFTs' in 2004 [1]. This is because a-IGZO TFTs are promising alternatives to the hydrogenated amorphous silicon (a-Si:H) TFTs due to their many advantages, such as a lower deposition temperature and higher field effect mobility compared to those of the a-Si TFTs [2][3][4].
The a-IGZO TFTs fabricated by the sputtering process, however, have an issue: defect sites can be generated in oxide films by high-energy target ions and the incorporation of Ar + ions during the sputtering process [5][6][7][8].
To alleviate the defect sites of a deteriorated film and to obtain sufficient switching properties, a-IGZO TFTs have required an annealing activation process at a high temperature over (300°C) after the deposition of a-IGZO active layers [9,10].
The thermal treatment at a high temperature, however, is not suitable for the formation of a-IGZO TFTs on a flexible polymer substrate, which generally has a low glass transition temperature [11,12]. Therefore, it is essential to develop a low-temperature fabrication process to solve the problem and to ultimately realize ideal flexible electronics.
Demonstrated herein is a low-temperature activation technique for a-IGZO TFTs by applying voltage bias to electrodes under 150°C. The electrical characteristics of a-IGZO TFTs activated with voltage bias are also investigated. Furthermore, the mechanisms of voltage bias activation are discussed based on the thermodynamic analysis of the a-IGZO TFTs using infrared microthermography.

Fabrication of a-IGZO TFTs
a-IGZO TFTs with an inverted staggered structure were fabricated on a heavily doped p-type Si wafer with 120nm-thick thermally grown SiO 2 . The a-IGZO active layer was deposited through radio frequency sputtering on a cleaned Si substrate using an IGZO target (In 2 O 3 :Ga 2 O 3 :ZnO = 1:1:1 mol%) at room temperature for 5 min, and the thickness of the resulting a-IGZO active layer was 40 nm. 200-nm-thick aluminum source and drain electrodes were deposited via thermal evaporation. The channel region was defined with a width (W) of 1000 μm and a length (L) of 150 μm. Figure 1(a) shows the schematic of the a-IGZO TFTs with an inverted staggered structure and voltage bias activation. For the fabrication of the conventional thermally activated a-IGZO TFTs that were used for reference, the devices were annealed at 300°C for 1 h in ambient air after the deposition of an active layer and source/drain electrodes. In the case of voltage bias activation, constant DC voltages were applied to the gate, source, and drain electrodes of the a-IGZO TFTs, respectively. The samples were annealed at 150°C with different gate voltage (V G ) bias conditions: V G = −100, 0, and +100 V. The source voltage (V S ) and drain voltage (V D ) were fixed: V S = 0 V and V D = 10.1 V, respectively. A photograph of the voltage bias activation process is shown in Figure 1(b).

Electrical measurements
The electrical characteristics of the devices were measured in a dark box under ambient conditions, using a semiconductor parameter analyzer (HP 4156C; Hewlett Packard, Palo Alto, CA). a-IGZO TFT measurements were carried out by inducing a gate voltage (V GS ) sweep from −30 to +30 V and a drain voltage (V DS ) of 10.1 V. High-resolution infrared micro-thermography analysis was performed to study the local-heating effect of a-IGZO TFTs.

Electrical and infrared micro-thermography analysis of the voltage-bias-activated TFTs
Figure 2(a) shows the transfer characteristics of the a-IGZO TFTs annealed at various temperatures (100, 150, 200, 250, and 300°C) for 1 h. The reference a-IGZO TFT annealed at 300°C shows sufficient transfer characteristics (e.g. field effect mobility (µ FET ), on/off current ratio) as it is recognized that thermal annealing at a high temperature ( ∼ 300°C) is important to control the properties of a-IGZO TFTs. Figure 2(b) shows the transfer characteristics of the a-IGZO TFTs fabricated with voltage bias activation. The optimized sample shows similar electrical characteristics in spite of a lower process temperature (150°C) compared to the reference one (300°C), and the optimized conditions were V G = +100 V and time = 1 h. The electrical parameter values of the reference and optimized samples, including the µ FET , on/off current ratio, V on , subthreshold swing (SS), and maximum trapped charge density (N max ), are arranged in Table 1. The µ FET was obtained from the I DS − V DS curves in the saturation   region (V DS ≥ V GS − V T ) using the equation below.
where C i and V T denote the gate capacitance and threshold gate voltage, respectively.
In the case where V G is −100 V, insufficient carriers were accumulated in the a-IGZO channel because of the repulsive force between the negative V G and the electron carriers. If V G is 0 V, it cannot attract as many electron carriers to the a-IGZO channel as when V G is +100 V. A +100 V V G , however, can attract sufficient electron carriers in the a-IGZO channel through the attractive force between the positive V G and the electron carriers. The sufficient electron carriers generate Joule heating at the a-IGZO channel region during voltage bias activation [13][14][15] because heat is produced when an electric current flows through a conductor, which is known as Joule heating, and because the amount of heat is proportional to the current flowing according to Joule's first law [16]. As a result, the additional Joule heat can compensate for the insufficient thermal energy of the low temperature (150°C), and can successfully activate a-IGZO TFTs at a low temperature.
The aforementioned electrical analysis results are in agreement with the infrared micro-thermography analysis results, as shown in Figure 3 [17]. When voltage bias was applied, the maximum temperature increase ( T max ) of the a-IGZO channel differed depending on the polarity of V G . As shown in Figure 3(b), T max increased up to 48°C with V G = +100 V. In contrast, as shown in Figure 3(c), T max was only 12°C when V G = −100 V. It was clearly observed that T max decreased along with V G . This was because the amount of Joule heat increased with the drain current, which originated from V G in accordance with Equation (1). A more positive V G attracts more electron carriers and generates more Joule heat. When V G = 0 V, it does not attract electron carriers, resulting in less Joule heat compared to the positive V G . A negative V G repulses electrons and generates the minimum Joule heat among the positive, zero, and negative V G .
The effect of voltage bias activation, however, cannot be explained by Joule heating alone because in this study, the Joule heating increased the T max of the a-IGZO channel to 48°C, and the 198°C total thermal energy that resulted from the simultaneous annealing at 150°C was insufficient to activate a-IGZO TFTs, as shown in Figure 2(a).
The a-IGZO film is composed of many electrons, protons, and ions of indium, gallium, zinc, and oxygen. The charged particles experience attractive or repulsive forces from the applied voltage bias according to the Coulombic interaction. It is generally known that the energy states of atoms and molecules are unstable, and that the probability of reaction increases when an external electric-field is induced in the oxide system [18]. The initial energy state of the a-IGZO film increases, and the film is likely to react and improve its weak chemical bonds by overcoming the activation energy barrier. In this situation, relatively lower thermal energy is required to overcome the activation energy barrier compared to the conventional activation process. That is, the voltage bias is not only the carrier source for Joule heating but is also the activation promotion process even at a low temperature (198°C) by driving the electric-field-induced molecules or atoms. Therefore, the voltage bias activation in this study can be achieved by Joule heating and by lowering the activation energy.

Conclusion
A new technology was developed to activate the a-IGZO TFTs at 150°C using electrical and thermal energy. In this study, with voltage bias, concurrent electrical and thermal treatment activated the a-IGZO TFTs at a low temperature, and caused it to exhibit superior electrical characteristics. By controlling V G , the electron carriers in the channel and drain currents can be controlled. Joule heating occurs with the drain current flow, and the T max of the a-IGZO channel increases along with V G . In addition, the applied voltage bias reduces the activation energy. The electrical energy compensates for the insufficient thermal energy at a low temperature (150°C), and the annealing temperature was decreased without degrading the electrical characteristics compared to the reference TFTs.

Disclosure statement
No potential conflict of interest was reported by the authors.

Notes on contributors
Heesoo Lee is currently pursuing a Ph.D. degree at the School of Electrical and Electronic Engineering of Yonsei University in Seoul, South Korea. She has been researching on thin-film transistors and the resistive random access memory based on metal oxide materials. He is currently a researcher at Korea Basic Science Institute. He has been conducting research on infrared micro-thermography, photothermal deflection spectroscopy, and local heat distribution analysis in the research center.