Parameter extraction and modelling of the MOS transistor by an equivalent resistance

ABSTRACT During the analysis of multi-transistor circuits, the need arises to evaluate the time delay or the power consumption of the circuit. Due to the complexity of the transistor model, several complicated equations arise from which a compact-form solution cannot be obtained and a suitable physical insight cannot be drawn. With this regard, two contributions are presented in this paper. The first one is a fully analytical parameter extraction approach to be applied on the MOS transistors. The second one is a quantitative method for simplifying the analysis of MOS circuits by modelling the MOS transistor by a suitable equivalent resistance adopting the time-delay or the power-consumption equivalence criteria. The parameter-extraction method is verified by using the extracted parameters in the derived expressions according to the second contribution. Compared to other representations, the agreement of the proposed model with the simulation results is very good.


I. Introduction
Modelling the MOS transistor is a very complicated task that was the topic of interest for myriad of researchers in the last few decades [1][2][3][4][5][6][7][8][9][10][11][12]. With the scaling down of the channel length of the MOS transistor, several second-order effects arise that cannot be neglected in today's deep-submicron devices including the velocity saturation, mobility degradation, changing the threshold voltage with the channel length and the channel width, to name such a few [1,13], and [14]. The main purpose of analysing digital CMOS circuits is to obtain first-order estimates for the propagation delay and the power consumption and develop physical insights into the parameters that affect the performance of the circuit significantly. It is expected that the analysis of circuits including several N-channel and P-channel MOS devices is a formidable task. As a result, very complicated expressions that cannot be solved in a compact form are obtained. As a simplification to the analysis of multi-transistor circuits, the MOS transistor can be represented by a suitable equivalent resistance. In this paper, circuits containing only MOS transistors and capacitors are referred to as transistor-like circuits while those that contain only resistances and capacitors are referred to as resistance-like circuits.
In this paper, two contributions are presented in the realm of modelling the MOS transistors in complicated circuits. The first one is a parameter-extraction method that is proposed for extracting suitable values for the parameters of the MOS transistor in accordance with the adopted model. The second one is a quantitative method for the evaluation of the equivalent resistance representing the transistor adopting one of the following two criteria; the 50% time delay of the resistance-like circuit is equal to that of the transistor-like circuit or the rise (or fall) times of the two circuits are equal. The equality of the 50% time delay guarantees that the propagation delays of the two circuits are equal while the equality of the rise or fall times guarantees that the short-circuit power consumption of the driven stage for the two circuits are equal. The rise (or fall) time is evaluated between the 90% and 10% time instants for the output waveform [15].
There are three important benefits that can be gained from representing the transistor by an equivalent resistance. The first and the most common one is the evaluation of the low-to-high and the high-to-low propagation delays of a CMOS circuit. In this case, the circuit simplifies to an RC circuit. The second aspect is the evaluation of the signal integrity by evaluating the rise or the fall times of the output waveforms of a CMOS circuit. The third aspect is the evaluation of the short-circuit power consumption which is related to the rise and fall times of the driving signal.
The remainder of this paper is organized as follows: A short discussion on the parameter extraction is presented in Section II along with the proposed approach. Section III presents the quantitative evaluation for finding the equivalent resistance of the MOS device considering the previously stated criteria preceded by a short discussion on the previous work in this realm. The simulation results are presented in Section IV. Finally, the paper is concluded in Section V.

II. Parameter extraction
Before describing the method of parameter extraction, the adopted MOSFET model is first presented.

A. Adopted MOSFET model
According to the adopted model, the current-voltage relationship in the subthreshold region of the NMOS devices is as follows [16]: where I 0n is given by i D is the drain current, µ 0n is the electron mobility, C oxn is the gate-oxide capacitance per unit area, W is the channel width, L is the channel length, (W/L) n is the aspect ratio, V thn is the threshold voltage, v GS is the gate-to-source voltage, v DS is the drain-to-source voltage, and V th is the thermal voltage which can be found from K, q, and T are Boltzmann's constant, the electronic charge, and the absolute temperature, respectively. Eq. (1) is valid for v GS < V thn . n n is the subthreshold-swing coefficient which is given by [17] n n ¼ 1 þ C d C oxn (4) where C d is the depletion-layer capacitance per unit area. When v GS is larger than V thn , the device operates in the triode or the saturation region. In the triode and saturation regions, the current-voltage relationships are and respectively. v satn is the free-electron saturation velocity and λ n is the channel-length modulation effect parameter. µ effn is the effective mobility of free electrons which can be expressed as [18] μ effn ¼ μ 0n 1 þ θ n v GS À V thn ð Þ (7) µ 0n is the mobility of free electrons at low vertical electric fields across the gate oxide and θ n is the mobility-degradation effect parameter. The edge of saturation is at v DS = V DSsat and is given by So, Eqs. (5) and (6) are valid for v DS < V DSsat and v DS ≥ V DSsat , respectively. Taking into account that the value of k is very small [19], its effect will be neglected here. Due to the drain-induced barrier lowering (DIBL) and body effects, V thn changes with v DS and v BS (the body-to-source voltage), respectively. This change can be modelled by the following relationship [20]: V thn0 is the threshold voltage at v DS = v BS = 0 V. γ n and η n are the linearized body-effect parameter and the DIBL parameter, respectively. For typical values of η n , the change of V thn with v DS can be safely neglected.

B. Previous work
Simply stated, the model is defined as the set of equations that properly emulate the behaviour of the component. In order to perform accurate and reliable IC design especially in the analog realm, accurate device models must be adopted. Device modelling can be performed by one of three approaches [21]. The first approach is a physics-based approach (also known as the analytical approach) in which the model parameters are closely related to the physical operation of the device and its operating regions. As a result, the extracted parameters are relatively very few and the results are rather inaccurate [14,22], and [23]. So, this approach is best suited to the application with simple device structures. The second approach is a best-fitting one (also known as the numerical approach) in which the parameters of the device model is fitted to the experimental results so that the accuracy will be enhanced. The third and final approach is a combination of these two approaches as a compromise between the accuracy and potential of physical interpretation. The parameter extraction is the process of finding suitable values for the parameters of the model such that the measurement results and simulation results will be close to each other [24]. Parameter extraction is an important step in order to ensure the accuracy of the simulation results and its closeness to the experimental results.
Another reason for the importance of the parameter extraction is as follows: In order to get a physical insight into the performance of the circuit at hand and to find first-order estimates for the performance metrics, a hand quantitative analysis should be performed. To ensure the potential of deriving simple and accessible compact forms, the parameters of the adopted model hardly exceeds ten. However, the models adopted for the device in the simulation program may contain hundreds of parameters. Thus, to obtain rather accurate results from the quantitative analysis, the accuracy of the adopted parameters must be guaranteed; hence the need for accurate parameter extraction. The link between the process characterization and the circuit simulation deserved a lot of research [25]. In fact, this point was the topic of many research papers.
The parameter extraction methods can be classified into two main approaches; optimization-based approaches and analytical approaches. According to the first one, the parameters extracted cover the complete operating range with suitable fitting algorithms applied but requires a relatively large time due to the need to deal with a large number of measurements [26] and [27]. The opposite is true for the second approach in which compact forms are derived for estimating the required parameters [28]. There are several methods for parameter extraction that vary in their accuracy and requirements in computer time [29].
Some of the techniques used with parameter extraction are associated with extracting accurate values for the parameters of the model used in the simulation with regard to the experimental measurements [30]. However, the parameter extraction performed here is associated with extracting accurate values for the parameters of the model used in the quantitative analysis from the simulation results, i.e., the approach presented for parameter extraction is such that the simulation results and analysis results will be close to each other. Specifically, due to the negligence of many short-channel effects in the adopted model in the analysis, this model is not appropriate for use with short-channel devices. The parameter-extraction process bridges the gap between the inaccurate simple MOSFET model and the rather accurate simulation results. The parameter extraction is performed using the MATLAB program. The procedure described in this paper for parameter extraction is simple, easy, fully analytical, and general in the sense that it can be applied on the experimental results equally well as on simulation results. Also, it can be applied on conventional silicon and GaAs devices.

C. Proposed parameter-extraction approach
In order to extract the parameters of the MOSFET model presented earlier, the MOSFET transistor is attacked by several excitation sources and the responses are determined by simulation. Using the simulation results, the necessary model parameters can be extracted. In order to guarantee that the extracted parameters are a good representation of the transistor performance over the whole operating region, several information at different biasing values are used. Since the procedure can be applied on NMOS and PMOS devices as well, it is illustrated for the NMOS devices only.

Extracting V thn0
Since the subthreshold current is not negligible, the i D -v GS characteristics does not intersect the v GS axis at the threshold voltage. So, the threshold voltage is taken here as the intercept of the linear portion of the i D -v GS characteristics with the horizontal axis as shown in Figure 1. Instead, for more accurate results, the i D -v GS characteristics can be plotted for several values of v DS conditional that the range swept for v GS is such that the transistor will operate in the saturation region. This is to ensure that Eq. (6) is valid and the required intercept is V thn0 . Then, the average of the extracted values is taken. The two functions, polyfit and mean, are used in finding the coefficients of the line that best fits the acquired data in MATLAB and the average of the extracted values, respectively.

Extracting λ n
As known, the Early voltage is simply the negative of the intersection of the i D -v DS characteristics with the horizontal axis and the channel-length modulation effect parameter is its inverse. So, the procedure of finding the threshold voltage can be applied equally well in this context. Several values of λ n can be found from the slopes of the i D -v DS curves at different values of v GS and then λ n is taken as their average. Again, the chosen values for v GS and v DS must ensure operating the transistor in the saturation region so that Eq. (6) will remain valid.

Extracting C oxn v satn
Since C oxn and v satn are multiplied by each other in Eq. (6) for the drain current in saturation, there is no way to find the value of each of them from the transistor characteristics. Fortunately, there is no need to find the value of each of them separately; there is a need to find their product. The same can be said about μ 0n and C oxn . Simply stated, find the drain current for certain values of v GS and v DS such that the transistor operates in the saturation region and Eq. (6) will be valid. Then, C oxn vs atn can be found from

Extracting k n ' and θ n
There are two methods for determining k n ' (the process-transconductance parameter which is equal to μ 0n C oxn ) and θ n . The two methods depend on Eq. (5). The first one depends on the deep-triode region in which v DS is much smaller than 2(v GS -V thn ). In this case, the i D -v DS relationship is almost linear with a slope equal to So, this slope can be found for any two values of v GS such that the transistor operates in the deep-triode region and k n ' and θ n can be determined. The other method is as follows: Since k n ' and θ n are not multiplied by each other in Eq. (5), a simple way for finding each of them is to find the drain currents for two different sets of values for v GS and v DS such that the transistor will operate in the triode region and Eq. (5) will be valid. From Eqs. (5) and (7), we can get from which k n ' and θ n can be determined. Although the first method is easier, it is less accurate due to neglecting the term, 0.5v DS 2 . So, the second method is adopted here.

Extracting γ n and η n
One way for finding γ n is to first find V thn0 as discussed previously by putting v BS equal to 0 V (with the change of V thn with v DS neglected), then finding V thn for any different value of v BS . The procedure is nothing but solving Eq. (9) with η n neglected. Another procedure for determining V thn0 , γ n , and η n is as follows: Plot V thn versus v BS and find the best straight-line fit to the plot; the slope of the resulting line is -γ n . It must be noted that the adopted value of v DS must be such that the transistor operates in the saturation region for all cases. This is in order to ensure the validity of Eq. (6) and that the extracted V thn is simply the horizontal intercept of the linear portion of the i D -v GS relationship. In fact, the effect of the term, η n v DS , in this case is just a shift in the value of V thn0 with the extracted value of γ n not affected. As will be seen shortly, the extracted value of η n is relatively small. So, the effect of the term, η n v DS , can be safely neglected in this case. The adopted value of v DS is 1 V. This procedure can be repeated for the relationship between V thn and v DS with v BS equal to 0 V. Refer to

Extracting I 0n and n n
The first direct method for finding I 0n and n n is to find the drain currents (i D1 and i D2 ) for two sets of values of v GS (v GS1 and v GS2 ) and v DS (v DS1 and v DS2 ) such that v GS is smaller than V thn and the transistor operates in the subthreshold region. From Eq. (1), we can get and In Eqs. (13) and (14), the body and the DIBL effects were neglected. After simple mathematical manipulations, we can write I 0n can then be determined from Eq. (13) or (14). Another method for determining I 0n and n n is from the slope of the drain current in the subthreshold region. From Eq. (1), if v DS is larger than V th such that the term, e À v DS = V th ð Þ , is much smaller than 1, we can write which is a straight-line equation with vertical intercept equal to ln I 0n -V thn /(n n V th ) and slope equal to 1/(n n V th ). So, I 0n and n n can be determined.

Extracting the internal capacitances
As known, some of the internal capacitances of the MOSFET transistor are voltage dependent. For simplicity, all the internal capacitances at all the transistor terminals will be treated as voltage independent; however, they are size-dependent [31]. In order to determine the parasitic capacitance at a certain terminal of the device, this terminal must be attacked by a proper voltage or current source with a properly series or parallel resistance, then a transient analysis is performed. In the following, two methods for extracting the values of the internal capacitances associated with the four terminals are discussed. Let us illustrate these two methods in detail with regard to the gate terminal taking into account that the same procedure can be applied equally well on the other terminals.
The first method depends on applying a current source with a constant value at the gate terminal of the MOS transistor with the other terminals grounded as shown in Figure 4. If the gate contains only a capacitive impedance, the gate voltage is expected to increase linearly with a constant charging rate equal to I/C G where I is the value of the charging current source and C G is the parasitic capacitance at the gate terminal. However, this is not the case as shown in Figure 5. Specifically, the instantaneous gate voltage, v G , increases with a rather constant rate only at the beginning of the charging process, then the charging rate decreases until v G saturates. The kink noted at the curve of Figure 5 before t = 0.1 ns can be attributed to the voltage dependence of C G on v G .
It can be concluded that the gate does not simply contain a capacitance only; it may contain inductance and resistance as well. For the channel lengths and the frequencies of operation of interest, the effect of the parasitic inductance can be safely neglected [32]. The equivalent circuit of the gate is thus as shown in Figure 6 where R G represents the parasitic resistance of the gate terminal. In order to decide on the nature of R G , current sources with different values are applied. The results are shown in Figure 7 for I equal to 1   nA, 10 nA, and 100 nA. It is obvious that increasing I not only speeds-up the charging process but also causes the steady-state gate voltage, let it be V G , to increase as expected. From Figure 6, V G is equal to IR G . However, the resulting values of V G does not increase in direct proportion to I; rather, it increases at a smaller rate. Specifically, the three values of V G are 0.47 V, 0.9 V, and 1.4 V for I equal to 1 nA, 10 nA, and 100 nA, respectively. So, R G is not constant but changes with V G in an inverse manner. This can be confirmed by Figure 8 which shows the i G -v GS characteristics and Figure 9 which shows the relationship between R G and v GS .
In order to find C G , the 50% time delay of the charging process must first be found. Due to the voltage dependence of R G , the differential equation describing the circuit of    Figure 6 is not a practical way. On the other hand, the current applied on the gate terminal is constant and thus as an alternative way, C G can be found from the following relationship: where t and ΔV G (the change of the gate voltage) can be found from the plot of v G (t) in the linear range. Refer to Figure 10 for the relationship between the extracted values of C G Figure 9. The relationship between R G and v GS. and the constant current-source value. Figure 11 shows the relationship between the aspect ratio and the extracted values of C G which confirms the direct proportionality. The second method for determining C G depends on applying a dc voltage source, V GG , in series with a resistance, R, on the gate terminal of the MOSFET transistor with the other terminals grounded as shown in Figure 12. If the voltage source is connected directly to the gate terminal, the gate voltage will be equal to V GG at all cases and there will be no way of discovering the gate equivalent circuit. If the gate contains a capacitance only, the steady-state gate voltage, V G , will be constant irrespective of the value of R. However, this is not the case; rather, V G decreases with increasing R as indicated in Figure 13. So, the gate contains a resistance, R G , as concluded in the illustration of the first method and illustrated in Figure 14. In order to avoid the effect of the voltage dependence of R G on v G , relatively small values of R are adopted so that the steady-state gate voltage will be constant at V GG . As a result, the instantaneous gate voltage is described by the following relationship: The 50% time delay is accordingly given by So, the gate capacitance can be evaluated from Figure 15 shows the extracted values of C G for different values of V GG . The estimated C G according to this method is thus close to that estimated by the first one. These two approaches can be applied on the other three terminals to find their associated parasitic capacitances taking into account these two points. First, the second method requires adopting a relatively small value for the serially connected resistance compared to the parasitic resistance of the terminal at hand so that the steady-state voltage at that terminal is equal to the applied one. This ensures that the voltage dependence of the parasitic resistance at that terminal will not affect the evaluation of the 50% time delay and hence the extracted capacitance at that terminal. The second point is that when determining the  values of C D , C B , and C S , the transistor must be deactivated in order to ensure that the applied current or voltage source charges the parasitic capacitance at the specified terminal at hand with no leaked current into that terminal. The list of the extracted parameters of the NMOS device to be used in the next section are shown in Table 1. The equality of C D and C S makes sense as the MOSFET is a bidirectional device with the drain and source terminals interchangeable.

A. Previous work
There were previous attempts for representing the transistor by an equivalent resistance; however, very limited previous work was reported in this realm. In fact, most of the previous work related to this realm lies in estimating the parasitic resistances of the transistors [31][32][33][34][35][36][37][38] or modelling the dependence of the current of the transistor on a certain voltage difference [39]. In [40], an empirical RC model for the transistor was  presented based on the equivalence of the time delay. The effective resistance according to this model depends on the type, size, and external connections of the transistor, the load, and the waveform of the input signal. One of the most simple methods is representing the transistor by a resistance equal to the ratio between the drain-to-source voltage and the drain current in a certain region of operation. This includes representing the MOS transistor as a voltage-controlled resistance if it operates in the deep-triode region; that is, with v DS ≪ 2(v GS -V thn ). The equivalent resistance, R, in this case is given by the ratio between the drain-to-source voltage and the drain current as follows [15]: Obviously, the term 0.5v DS 2 was neglected in Eq. (21). However, this representation is valid only for a limited range of voltages; specifically for v DS < 0.2(v GS -V thn ) which is typically smaller than 0.15 V for deep-submicron CMOS technologies. Alternately, in the saturation region, the equivalent resistance can be estimated as the ratio between v DS and i D with both v DS and v GS equal to the power-supply voltage, V DD [41]; Since the device usually operates part of the time in the saturation region and another part in the triode region, a combination of these two regions can be performed by evaluating the equivalent resistance at the edge of saturation with v GS = V DD and v DS = V DD -V thn as follows [41]: In [15], an empirical estimation was adopted for the equivalent resistances of the NMOS and PMOS devices in estimating the charging and discharging time delays with the inverse dependence between the equivalent resistances and the aspect ratios, (W/L) n and (W/L) p , taken into account. According to this estimation, the equivalent resistances of the NMOS and PMOS devices are given by and respectively. It must be noted that the factors, 12.5 and 30, adopted in Eqs. (24) and (25) depend on the technology. It has been found that these values apply well for a number of processes including the 0.25 μm, 0.18 μm, and 0.13 μm CMOS processes [42]. Although estimating the performance of the circuit using these estimated equivalent resistances is simple, several parameters were not taken into account such as the threshold voltage and the short-channel effects.
In [43], three methods were proposed for estimating the equivalent resistance of the MOS transistor. The first one is finding the ratio between the average drain-to-source voltage and the average drain current, i Davg , with the average for each of them evaluated simply as the arithmetic average for the two values at the onset and end of the mode of operation of interest. The drawback of this method is that the estimated equivalent resistance depends on the output voltage of the circuit, which is not a transistor parameter; this is really the case with CMOS-transmission gates. The second method is using integration for estimating the average drain current as follows: The third method depends on using the following integration [31] and [44]: where i D is to be expressed as a function of v DS . Although these compact forms for the equivalent resistance is more accurate than the formula of the deep-triode region, the propagation delay as well as the power consumption estimated in these ways are relatively inaccurate.
In this paper, more accurate compact forms are derived for the equivalent resistance such that each of the propagation delay and the rise and fall times evaluated using the equivalent-resistance circuit and the original circuit containing the MOSFET devices are equal. The main advantages of the proposed equivalent-resistance representation are: 1. The availability of a compact mathematical model with a relatively small number of components.
2. The accuracy is better in estimating the propagation delay and the power consumption.
3. The derivations of all the compact forms are straightforward with no need to deal with numerical analysis techniques, so it is relatively fast.
4. Finally, the derived expressions can be applied to any CMOS technology by substituting the values of the model parameters in the respective derived resistance expressions. There are neither empirical nor fix-up parameters that certainly depend on the adopted technology.
However, all these merits come at the expense of more complicated expressions; an expected demerit, since the accuracy is usually traded-off with simplicity. Also, since the derived resistance expressions are based on performance metrics related to digital signals, it must be noted that they are not suitable for use with analog signals.

B. Quantitative analysis
There are four cases that can be considered in the evaluation of the propagation delay in digital CMOS circuits. The first one is the discharging of a load capacitance, C L , through a single NMOS device. The second case is the discharging of C L through serially or parallel connected NMOS devices. The third case is the discharging of C L through the pull-down network (PDN) while there is a contention current from a PMOS load. The fourth and final case is the charge sharing between two capacitors through an NMOS device. The analysis for finding the equivalent resistance is performed for the NMOS case; PMOS-case expressions can be obtained in the same way with the parameters of the NMOS replaced by the PMOS ones.
Throughout the analysis performed in this paper, the load capacitance will be assumed to be much larger than the internal capacitances of the MOS transistors. This assumption is justified by the following reasoning: The load capacitance comprises three subcomponents; those due to the internal capacitances of the transistors in the driving stage, the interconnection line between the driving and the driven stages, and those due to the internal capacitances of the transistors in the driven stages. Taking into account that the percentage of the delay due to the interconnection lines increases with technology scaling [20,[45][46][47][48], the parasitic capacitances due to the transistors of the driving stage can be safely neglected.
According to the proposed equivalence, the equivalent resistance neither will be evaluated using an integration nor will depend on certain voltages or currents in the circuit. The parameters of [49] are adopted in the following plots and all the devices are assumed to be minimum-sized unless otherwise specified. The parameters extracted using the previously presented extraction approach is used in the following analyses.

The first case
Now, refer to Figure 16 (a) for a simple NMOS transistor discharging a capacitance, C L , which is initially charged to V DD and to Figure 16 (b) for its equivalent circuit in which the NMOS device is replaced by an equivalent resistance, R. This is typically the case in the CMOS inverter when the input voltage is equal to the power-supply voltage, V DD . The purpose now is to find an expression for R in terms of the device dimensions and process parameters such that the 50% propagation delay, t 50% , or the fall time, t f , of the transistorlike circuit are equal to their counterparts of the resistance-like circuit. t f is evaluated as the difference between the 10% and 90% points, t 10% -t 90% . During the time interval of the discharging of C L , M N operates in either the saturation or the triode region depending on v CL (the voltage across C L ). In the saturation region, the discharging process is described by the following differential equation (where v DS is substituted by v CL ): M N leaves the saturation region at t = t sat when v CL reduces below V DD -V thn . So, When v CL becomes smaller than V DD -V thn , M N operates in the triode region and the discharging process of C L is described by the following differential equation: The solution of Eq. (31) is The integration was performed taking t = 0 as the instant of time corresponding to the entrance of the device in the triode region. Accordingly, the initial value of v CL was taken equal to V DD -V thn . The time interval from the instant at which M N enters the triode region to that at which v CL equals V DD /2, t triode , is thus t 50% is the sum of t sat and t triode . So, t 50% is given by In case V DD is smaller than 2V thn , V DD -V thn will be smaller than V DD /2 and M N operates in the saturation region for the time interval extended from t = 0 to t = t 50% . In this case, t 50% is evaluated from Eq. (29) to be t 90% and t 10% can be obtained with the aid of Eqs. (29) and (32) corresponding to v CL = 0.9V DD (provided that V thn > 0.1 V DD ) and 0.1V DD , respectively, as and So, t f is given by On the other hand, the voltage across C L in the circuit of Figure 16 (b) is given by So, the corresponding three time instants, t 50% , t 90% , and t 10% are given by where m is equal to 0.5, 0.9, and 0.1, respectively, for these time instants. If the 50% delayequality criterion is applied, then the equivalent resistance, R, is given by If the fall-time equality criterion is applied, then R is given by Refer to Figures 17 (a) and (b) for the plots of the relationships between the equivalent resistance of the single NMOS device evaluated according to the 50%-delay equivalence and the aspect ratio and the threshold voltage, respectively.

The second case
Now, we consider the case of the discharging of C L through serially or parallel connected NMOS devices. This is the case in wide fan-in CMOS NAND or NOR gates. In case of parallel connection of NMOS devices, the preceding analysis applies with replacing the channel width or the aspect ratio by the same parameter multiplied by n where n is the number of parallel NMOS devices. On the other hand, two scenarios are considered for the case of series connection; two and larger than two serially connected NMOS devices. For simplicity, the effects of the internal capacitances and the body effect are neglected here. Refer to Figure 18 (a) for illustration of the case of discharging through two serially connected NMOS devices. There are three time intervals for the discharge of C L ; both M 1 and M 2 are in saturation, M 1 is in triode and M 2 is in saturation, and both M 1 and M 2 are in triode; note that since the drain voltage of M 2 is at a higher voltage than that of M 1 , M 1 enters the triode region before M 2 does. During the first time interval, the discharging process can be described by where v DS1 and W n1 are the drain-to-source voltage and the channel width of M 1 ; v DS2 and W n2 are their counterparts for M 2 . Since the sum of v DS1 and v DS2 equals v CL , we can get v DS2 in terms of v CL as Figure 18. Discharging of C L through (a) two transistors, (b) more than two transistors, and (c) equivalent circuit of (b) when all the devices except M n operate in the triode region.
After substituting into Eq. (43), we get where a 1 and b 1 are given by and respectively. M 1 leaves the saturation region at t = t 1 when v DS1 equals V DD -V thn . This instant of time corresponds to v CL = (V DD -V thn + a 1 )/(1 -b 1 ). So, The second time interval can be treated in a similar manner. In the second time interval, the discharging process can be described by the following equation: where the term 0.5v DS1 2 was neglected. (W/L) 1 is the aspect ratio of M 1 . After simple mathematical manipulations and neglecting the term v DS1 v DS2 and using the fact that the sum of v DS1 and v DS2 is equal to v CL , we get where a 2 is given by (51) v DS1 can be substituted in terms of v CL from Eq. (50) into Eq. (49) with the result that Let a 3 and b 3 be given by respectively. So, Eq. (52) can be written as Taking into account that the second time interval begins when v CL equals (V DD -V thn + a 1 )/(1 -b 1 ) and ends (at t = t 2 ) when v CL equals V DD -V thn , we get the solution of Eq. (55) as For the third time interval, the discharging process can be described by After simple mathematical manipulations and neglecting v DS1 with respect to V DD -V thn , we get The latter approximation is justified by the fact that v DS1 is relatively small in this time interval. v CL is consequently given by After substituting v DS1 from Eq. (60) into Eq. (58), we get The solution of Eq. (61) is v CL equals V DD /2 when t = t 3 (estimated from the beginning of the third time interval). So, t 50% is the sum of t 1 , t 2 , and t 3 . t 90% and t 10% can be evaluated with the aid of Eqs. (45) and (62) corresponding to v CL = 0.9V DD and 0.1V DD , respectively. So, and The equivalent resistance can be simply found by equating the time delay or the fall time with the corresponding equations for the equivalent RC circuit. Now, consider the scenario of the discharging of C L through n transistors where n is larger than two (refer to Figure 18 (b) for illustration). There are two time intervals in this case; the first one corresponds to the operation of all the devices except M n in triode region and the second one corresponds to the operation of all the devices in triode region. Figure 18 (c) illustrates the representation of all the devices except M n by a resistance, R triode . In order to find an expression for R triode , let the triode-region operated devices be represented by a single equivalent device with an aspect ratio of (W/L) n /(n -1); the iv relationship of the equivalent device is given by where the term, 0.5v DS 2 , was neglected. Now, the equivalent resistance of the device, R triode , is simply taken as the ratio between v DS and i D in Eq. (66) with v GS substituted by an average value, v GSavg . In order to find v GSavg , let the average value of v CL , V DD /2, be equally divided between the (n -1) devices. This results in Now, the discharging of C L can be described by in which the term, λ n v DS , is neglected here. So, M n leaves saturation at t = t sat which can be shown to be given by In the same manner, when M n leaves saturation, all the n devices can be represented by a resistance with v GSavg = (3 n + 1)V DD /4 n. So, t 50% in this case is given by t 50% = t sat + t triode where t triode (corresponding to v CL = V DD /2) is given by t 90% can be shown to be given by (from Eq. (69)) t 10% can be found in a similar way in the second time interval as The equivalent resistance can thus be found in a manner similar to the previous case. Figures 19 (a), (b), and (c) portray the relationships between the equivalent resistance of a stack of NMOS devices and their aspect ratios, their threshold voltages, and the number of the transistors, respectively. n is assumed to be equal to 8 unless otherwise specified.

The third case
The third case to be considered is that when both the pull-up network (PUN) and the PDN are active. This is the case in the pseudo-NMOS logic-circuit family. Refer to Figure  20 (a) for the inverter in this family. When v in is equal to 0 V, M N is deactivated and the load capacitance, C L , charges to V DD which is the output-high voltage, V OH . If v in is equal to V DD , M N is activated; however, the output-low voltage, V OL , is not equal to 0 V in this case due to the contention current of the always-activated PMOS transistor, M P . In this case, the equivalent circuit is as shown in Figure 20 (b) where R N and R P are the equivalent resistances of M N and M P , respectively. It is now required to find the expressions of R N and R P . Towards that end, the two circuits of Figures 20 (a) and (b) are analysed with the expressions of the high-to-low propagation delay, t PHL , and the fall time, t f , equalized for the two circuits. Figure 21 shows the definitions of the 90%, 50%, and 10% points for this case. Evaluating the t 10% point is based on the assumption that the NMOS device has a sufficient strength to pull down the output voltage, v out , to 0.1V DD or less. The circuit of Figure 20 (b) can be described by the following equation:  Figure 21. A qualitative plot for indicating the definition of the 90%, 50%, and 10% points [15].
v CL (0) is equal to V DD for the initially charged capacitance. The solution of Eq. (75) is t 50% , t 90% , and t 10% can be derived with the aid of Eq. (76) by substituting the corresponding values of v CL . So, and where V OL was substituted by V DD R N /(R N + R P ). The fall time, t f , is thus Now, refer to Figure 20 (a). Due to the change of the mode of operation of M N and M P between saturation and triode, the discharging process of C L can be divided into three time intervals as shown in Figure 22 and Table 2. The discharging process of C L can be described in region I by the following differential equation: where the term, 0.5(V DD -v CL ) 2 , was neglected in the term of the current of M P . This negligence was justified by the fact that during region I, the voltage across C L has a relatively large value and thus the voltage across M P has a relatively small value. The solution of Eq. (81) is where a and b are given as respectively. t 90% can be found from Eq. (82) as The time instant, t 1 , at which M N leaves the saturation region and enters the triode region can be found by substituting v CL by V DD -V thn into Eq. (82) In order to simplify the analysis in region II, the average currents of M N and M P , i DNavg and i DPavg , are adopted. Each of these two currents is the average of the two currents at the onset and end of region II. So, region II can be described by the following differential equation:  The solution of Eq. (87) is According to Eq. (88), t = 0 is the instant of time at which M N enters the triode region. So, t 50% is the sum of two times as follows: where t 21 is the time at which v CL reaches the level corresponding to the 50% point; V OL + 0.5 (V DD -V OL ). So, M N leaves region II at time t = t 2 which is given by The third region, III, can be described by the following differential equation: The term, 0.5v CL 2 , was neglected in Eq. (92). This negligence was justified by the fact that during region III, the voltage across C L has a relatively small value. The solution of Eq.
where c and d are given by and respectively. t 10% is the sum of three times, t 1 , t 2 , and the time at which v CL reaches V OL + 0.1(V DD -V OL ) in region III. So, Now, in order to evaluate R N and R P , we will adopt the assumption that the NMOS device has a much larger strength compared to the PMOS device; that is, R N is much smaller than R P . Adopting this assumption and neglecting R N with respect to R P in Eq. (77) results in where t 50% is given by Eq. (89). Now, from Eq. (80), we get the expression of R P as where t f is given by the difference between the two times of Eqs. (96) and (85). Now, refer to Figures 23 (a) and (b) for the plots of the relationships between the equivalent resistance and the aspect ratio and the threshold voltage of the NMOS device, respectively. In these results, the following parameters of the PMOS transistor which were extracted using the approach presented in the previous section are adopted: V thp = −0.34 V, k p ' = 280 µA/V 2 , λ p = −0.45 V −1 , and C oxp v satp = 650 A/Vm. The aspect ratio of the PMOS device was assumed to be two.

The fourth case
The fourth and final case to be considered in this paper is that of the charge sharing between two capacitors through a MOS transistor. This case can be found in singletransistor single-capacitor dynamic-random access memories in which the charge is shared between a cell-storage capacitor and a bitline-parasitic capacitance [50], in domino logic in which the charge is shared between the dynamic-node capacitance and one of the internal parasitic capacitances in the PDN [15], or in circuits that depend on charge steering in their operation [51]. The latter circuits can be found in latches, demultiplexers, clock-and-data recovery circuits, and analog-to-digital converters. For illustration, refer to Figure 24 (a) for two capacitors, C 1 and C 2 , sharing their charge through the access device, M N . Figure 24 (b) represents the equivalent circuit of Figure 24 (a) in which the equivalent resistance of M N , let it be R, is shown. It is now required to find the expression of R. Towards that end, the following assumptions are made: 1. C 1 and C 2 may be different; 2. the initial voltage of C 1 is larger than that of C 2 ; that is, v C1 (0) > v C2 (0); 3. neither C 1 nor C 2 is initially discharged; 4. the initial voltage of C 1 is larger than V DD -V thn ; and 5. the steady-state voltage at the end of the charge sharing between C 1 and C 2 is smaller than V DD -V thn .
In spite of the previous assumptions, the analysis performed is general and the 50% criterion is adopted in deriving the expression of the time required for charge sharing and evaluating R. The 50% point is defined here as the time required for the voltage across C 1 to reach the average voltage of the initial and final voltages across C 1 . Refer to Figure 25 for illustration. According to this figure, t 50% is given by where t sat and t triode are the time intervals corresponding to the operation of M N in the saturation and triode regions, respectively. Using the principle of charge conservation [15], the final voltage of C 1 and C 2 at the end of the charge sharing is given by The charge-sharing problem can now be described as follows: Given C 1 , C 2 , v C1 (0), and v C2 (0), find the expression of R. At the onset of the charge sharing, M N operates in the saturation region. So, this time interval can be described by the following differential equation: Figure 24. The circuit schematic representing the charge sharing between C 1 and C 2 and (b) its equivalent circuit when representing the access device by an equivalent resistance, R. Figure 25. The voltage waveforms across C 1 and C 2 upon charge sharing between them.
In order to simplify the analysis, v C2 is substituted by its average value which is given by The solution of Eq. (101) is So, t sat is given by Now, the triode-region operation of M N can be described by the following equation: in which v C2 was substituted by its average value also and the term 0.5v DS 2 was neglected as it has a very limited value in the triode region. The solution of Eq. (105) is So, t triode is given by Note that the previous estimation was based on the assumption that the average value of v C1 , V C1avg , is smaller than V DD -V thn . If this is not the case, then (with the aid of Eq. (104)), t 50% will be given by Figure 26. The relationships between the equivalent resistance of the access device and its (a) aspect ratio and (b) threshold voltage.
Now, to find the relationship between t 50% and R, refer to Figure 24 (b). This circuit can be described by the following equation: The solution of Eq. (109) is where A 1 and A 2 are given by respectively. So, t 50% is given by R can be found by equating Eqs. (108) and (113). Now, refer to Figures 26 (a) and (b) for the plots of the relationships between the equivalent resistance of the access device and its aspect ratio and its threshold voltage, respectively.

IV. Simulation results
In this section, the analysis performed in the paper is verified and the estimated 50% time delay, from which the equivalent resistance is evaluated, will be compared with the simulation results and also with other time delays estimated by other previously proposed equivalent MOSFET resistances. The parameters of [49] are adopted for the 45 nm CMOS Berkeley predictive-technology model (BPTM) in the simulation. The parameters extracted from this model will be adopted in plotting the derived equations with all the devices assumed to be minimum-sized except the PMOS device which has an aspect ratio of two. When citing [41] in the comparison, Eq. (23) is adopted. The load capacitance will be assumed to be equal to 10 fF. Figures 27 (a) and (b) exhibit the estimated 50% time delay for the first case of a single NMOS device discharging an initially charged load capacitance. The estimated time delay according to the equivalent resistance of [42] does not depend on V thn and is equal to 0.086 ns. It is apparent that the performed analysis not only gives the most accurate results compared to simulation but also the best agreement with the trend of the decrease or the increase of the time delay with (W/L) n and V thn , respectively. Figures 28 (a) and (b) are the counterparts of Figures 27 (a) and (b) for the case of the NMOS stack with n = 8. Although the difference between the proposed model and the simulation results is perceptible, the adopted model gives the more accurate results compared to the other three models.
Figures 29 (a) and (b) give the results for the case of contention between an NMOS device and a PMOS one when discharging an initially charged capacitance. Finally, Figures 30 (a) and (b) give the results of the case of charge sharing between two capacitors with capacitances that are assumed to be 50 fF and 100 fF and are initially charged to 1 Figure 28. The relationships between the 50% time delay and the (a) aspect ratio and (b) threshold voltage according to the performed analysis, previous analyses, and simulation for the case of an NMOS stack. Figure 29. The relationships between the 50% time delay and the (a) aspect ratio and (b) threshold voltage according to the performed analysis, previous analyses, and simulation for the case of contention current between an NMOS device and a PMOS one when discharging an initially charged capacitance.
V and 0.35 V, respectively. The equivalent resistance of [42] gives the more accurate results in this case with respect to the change of the aspect ratio of the NMOS device as shown in Figure 30 (a). However, the results of this work are not that bad.

V. Conclusions
In this paper, a fully analytical parameter-extraction approach was proposed and applied on the MOSFET devices. The proposed parameter-extraction procedure is simple, easy, fully analytical, and general in the sense that it can be applied on the experimental results equally well as on simulation results. Also, it can be applied on conventional silicon and GaAs devices.
The equivalence of the MOS transistor with a resistance was discussed with the expression of the equivalent resistance derived for four cases. The four cases considered were that of a single NMOS device discharging a capacitance, a stack of NMOS transistors discharging a capacitance, a capacitance discharging through an NMOS transistor with a contention current from a PMOS device, and a charge sharing between two capacitors through an NMOS device. The two criteria considered were the equivalence of the propagation delay and the fall time between the transistor-like circuit and their counterparts in the resistance-like circuit. The MOS model adopted in this paper was rather simple; yet, took some of the short-channel effects into consideration. Compared to other existent resistance models, the proposed analysis exhibited a very good agreement with simulation results.

Disclosure statement
No potential conflict of interest was reported by the authors. Figure 30. The relationships between the 50% time delay and the (a) aspect ratio and (b) threshold voltage according to the performed analysis, previous analyses, and simulation for the case of charge sharing between two initially charged capacitors through an NMOS device.