An analytical design and analysis of a high gain switched inductor voltage multiplier cell power converter

The proposed modified higher gain boost converter employs switched Inductor and multiplier cell-based voltage boosting techniques, as the paper represents. This converter is modelled to enhance the static gain and efficiency. As the designed topology has an incessant source current at its input side, it is ideal for solar PV applications. With a power capacity of 100 W, the proposed topology is designed to work on 24 V source input and 200 V load/output voltage. The load voltage is maintained by a PI controller, which achieves the highest efficiency of 92% under rated load conditions. The converter’s transient performance with the controller is investigated under various situations, including supply voltage variation, reference voltage variation, and load power variation. Finally, the designed converter’s experimental model is created to evaluate the simulated and conceptual results.


Introduction
The usage of non-conventional energy sources is growing daily owing to the adverse effects of conventional energy sources.Hence renewable energy is used in the production of electricity.Renewable energy such as solar photovoltaic is used popularly.It can supply in the range of 10 KW, but the issue is that it produces low output voltage.Hence, a boost converter improves the voltage to higher levels.The issue with boost converters is that they have less voltage gain and higher switching stress [1].Over the years, research has resulted in many circuit designs that can be applied to microgrids that utilize boost converters.As a result, high-gain DC-DC boost converters were required.
Boost converter structures based on impedance networks are developed using one switch with identical capacitors and Inductors [2].The interleaved converter topologies are employed to reduce the switching stress.The floating interleaved boost converter possesses two modules linked in a cascaded manner at the output and parallel at the source side to produce a less voltage gain with reduced switching loss [3].The converters presented in Refs [4][5][6] have a multiplier cell with the boost converter to generate a high static voltage gain.When the multiplier cell is used with a classic stepup converter, the load side voltage is twice that of the classical step-up converter without an increase in the switching voltage.Switch conduction losses are reduced by lowering the drain-source voltage [4].When the multiplier cell works as a clamping circuit for regeneration, it reduces the problem of EMI generation.When the multiplier cell is combined with the step-up converter, it gives more static gain and less duty cycle [5].The controlled inverter, which is used instead of a single transistor, reverses the multiplier input current to reduce the power loss by the capacitors.In this circuit, the capacitance of the voltage multiplier cell capacitors is also reduced [6].Many research have been done to introduce the non-isolated DC-DC power converter topologies.Boosting of input voltage is done by switched Inductor.The concept of capacitor charging in parallel and getting discharged in series is reported in Ref. [7].This converter has three switches and is operated by two duty ratio.The gain is achieved with a duty ratio of 0.8 to 1; however, getting such a gain is difficult [8].
A capacitor-diode network employed in the nonisolated converters improves the output voltage.The converter has two switches controlled by a single gating signal [9].For further increase in gain, several boost and quadratic converters are used [10].Operating the power switch with a duty ratio greater than 0.7 improves the static gain of the converter [11].A voltage doubler circuit employed in the non-isolated converter topology doubles the output voltage, thereby improving the voltage gain [12].High-gain extendable power converters structures are presented in Refs [13,14] and use two or more semi-conductor switches to augment the voltage gain.In extended stages, the component count increases, but voltage gain is not changed as much.DC-DC step-up power converters with high voltage gain are employed in real-time situations such as UPS, lamp ballasts, traction and medical applications [15,16].The significant limitations of isolated DC-DC converters are transformer core saturation and low efficiency [17,18].The switched capacitor is used with a step-up converter to give more gain in voltage.The continuous input current is obtained without maintaining a highduty cycle [19].The converter is designed to supply two different voltage levels, one for low-level loads and the other for high-level loads, which are very suitable for DC micro-grid applications [20].
There is great demand for DC-DC power converters having improved voltage gain with innovative characteristics.This work presents a new lofty step-up DC-DC converter topology that includes a switched inductor, multiplier cell, and only one switch.In addition, the voltage boosting techniques enhanced output voltage with less switching stress, thereby increasing efficiency.

Proposed switched inductor-voltage multiplier cell high gain (SI-VMHG) converter topology
The proposed SI-VMHG converter model is designed by integrating the voltage boosting cells such as the switched Inductor and multiplier to augment the voltage gain.The SI-VMHG converter uses a single power switch S, six power diodes D 1 to D 6 , high frequency operated inductors L 3 , L 2 , L 1 and capacitors C 1 to C 5 .The resistive load is considered for analysis purposes.The pictorial representation of the SI-VMHG topology is exposed in Figure 1.The SI-VMHG converter is designed by taking into consideration of the subsequent hypothesis.The power switches and power diodes are expected to be ideal; output capacitance has a significant value to get ripple-free output voltage.

Operating modes of proposed SI-VMHG converter
Depending on the gating pulse, the proposed model operates in five ways.The switching characteristics of the SI-VMHG model can be found in Figure 2.
Mode 1: For the time range [t 0 -t 1 ], the power semiconductor switch S is turned ON.The D 2 , D 3 , and D 5 power diodes are biased in the forward direction and D 1 , D 4 , D 6 , D 7 , and D 8 diodes are biased in the reverse direction.The L 1 and L 2 inductors are charged with the source voltage V in .The inductor L 3 and capacitor C 1 get charged due to capacitor voltage C 2 .The capacitor C 5 supplies the energy to the load resistor R. The current direction during mode 1 is pictured in Figure 3.The voltage across the L 1 , L 2 and L 3 inductors are found using KVL is portrayed in 3 and are expressed in Equations ( 1)- (4).
Mode 2: Power switch S is in ON position during time [t 1 -t 2 ].The D 2 , D 3 , and D 8 power diodes are in a conducting state, and D 1 , D 4 , D 5 , D 6 , and D 7 diodes are in a non-conducting state.The L 1 and L 2 inductors get charged to the V in .The capacitors C 3 and C 4 release its energy, whereas the capacitor C 1 gets charged.The capacitor C 5 supplies the power to the load and is displayed in Figure 4. Using Kirchhoff's Voltage Law, the voltage across the L 1 , L 2 and L 3 inductors are found and given in Equations ( 5)- (7).D 3 diodes are in conduction mode, and the remaining power diodes are in OFF condition.The L 1 and L 2 inductors continuously store its energy while the capacitor C 5 discharges its charge to the resistor R. The flow of the current path direction is presented in Figure 5.The L 1 and L 2 inductor voltage expressions are specified in Equations ( 8)-( 11) after applying the KVL.
Mode 4: During the period [t 3 -t 4 ], the semiconductor switch S is in turned OFF position.The D 1 , D 4 , D 6 , and D 7 power diodes are forward-biased, and D 2 , D 3 , D 5 , and D 8 the diodes are reverse-biased.The capacitor C 2 is charged by discharging the L 1 and L 2 inductors.Similarly, the L 3 inductor, C 2 , C 3 and C 4 capacitors are charging due to capacitor C 1 .The current flow in the circuit is depicted in Figure 6.The capacitor C 5 discharges its stored energy through R. The voltage across the passive elements is given in Equations ( 12)- (16).
Mode 5: For the duration of [t 4 -t 5 ], the semiconductor switch S is in turned OFF position.The D 1 , D 4 , D 6 , and D 7 power diodes are forward-biased, and D 2 , D 3 , D 5 , and D 8 the power diodes are reverse-biased.Now, L 1 and L 2 inductors are discharged, and L 3 inductor is discharged in a positive direction.The C 2 , C3, and C 4 capacitors start to charge, and C 1 and C 5 capacitors start to discharge.The direction of the current path is displayed in Figure 7, and the voltage expressions are given in Equations ( 17)- (20).
The static gain expression of the suggested SI-VMHG converter is determined using Equation (21) and stated in Equation ( 22) using the volt-sec balancing method.where I, II, III, IV, and V are operating modes

Design of inductor
The inductors L 1 and L 2 ripple current during the turnon period of the switch is computed as The derived Inductors L 1 and L 2 values are based on source voltage (V in ), duty ratio (d), switching frequency (f s ) and inductor ripple current ( I L ), the inductor values are given as per equation given in ( 23) The average currents through the inductors L 1 and L 2 are expressed as The inductor L 3 value depends on the capacitor voltage and is designed by using Equation ( 24)

Capacitor selection
The energy stored in the input inductors during mode 5 is transferred to the multiplier capacitor C 2 through diode D 4 .The current variations in the diode D 4 are reduced linearly because the capacitor C 2 voltage decreases and maintains constant voltage applied to the resonant inductor.The capacitors C 3 and C 4 get charged in mode 5 where the power switch S is in turnoff condition.The energy stored in the capacitors is expressed as The final expression for the selection of capacitors is based on switching frequency (f s ), duty ratio (d), source voltage (U in ), output voltage (U 0 ) and ripple voltage ( U c ).The capacitor C 1 -C 5 values are selected based on Equations ( 29)-(32).

Power loss analysis
The power loss analysis of any converter topology is considered more important because the internal parasitic parameters are included.The internal parasitic resistance of inductor, capacitor and diode are considered for power calculations.The powers consumed by each of the components are computed as below.Let us consider the value of R L is 10 mΩ.Power Loss due to inductor: The power loss of the inductors L 1 , L 2 and L 3 is derived and given in (33) The value of I L1 , I L2 and I L3 values are calculated using Equations (25) and the power loss is obtained as 1.65 W.
Power Loss due to Capacitors: The power loss of the capacitors is computed by using Equation (34).The  value of R C is 10 mΩ.
The RMS current values of the capacitors I C3 , I C4 and I C5 are calculated using the following equations: The computed power loss of the capacitor is 2. Likewise, the forward voltage drop loss of the diode is given in Equation (39).Let, V f is 0.74 V.The computed power loss of the diode is found to be 3.69 W.
Power Loss Due to Switch: The power loss of the switch is due to switching loss and conduction loss.The power loss associated with the on-state resistance of the switch is given in (41).Let, R s is 27 mΩ.
The switching loss associated with the switch is given in (42).Let, t on + t off is 74.9 ns.
where I S_RMS = 16dI 0 2 /(1 − d) 2 .The computed power loss of the switch is 2.35 W. Thus, the total power loss of the proposed high gain converter is calculated by using the following equation: P L_T = P L + P C + P D + P S = 9.87 W (43) The efficiency of the proposed converter is expressed as

Investigation of the proposed SI-VMHG converter with previously designed converter topologies
The static voltage gain, component count, stress in the semiconductor devices, and efficiency of the SI-VMHG converter parameters are compared with various existing converters are tabulated in Table 1.In comparison with the step-up converter, the SI-VMHG topology achieves a 77% increase in voltage gain.The static gain of the converters against the duty ratio is drawn and is shown in Figure 8.The diode switching stress of the SI-VMHG converter with the converter presented in Ref.
[2] is equal, but it is 24% less when compared with the converter in Ref. [1].The amount of switching components in the SI-VMHG converter is 50% lesser than the converter in Ref. [12].The reduction of component counts leads to a reduction in the power density of the circuit.The simulated efficiency of the proposed SI-VMHG model under rated load conditions is 92%.

Results and discussions of simulation
The proposed converter topology is created in MAT-LAB using the Matlab Simulink tool.It is designed to operate with a 24 V source voltage, a 200 V load voltage, and a 100 W load power.Based on Equations ( 23)-( 28), the values of the power circuit components such as inductors and capacitors are calculated and displayed in Table 2.The voltage at the converter's output varies for duty ratio, but the converter should maintain the same voltage of 200 V at the output side.The constant load voltage is achieved by using the PI controller.The controller parameters are regulated in such a way as to maintain the voltage at the output constant.The Z-N tuning methodology is adopted to obtain the proportional gain k P and integral gain k i values.The block diagram representation of PWM generation using the PI controller is shown in Figure 9.The closed-loop MAT-LAB simulation of the SI-VMHG converter is pictured in Figure 10.The simulated input and load voltage, current, and power graphical waveforms are shown in Figure 11.The controller maintains a steady voltage of 200 V in the load side of SI-VMHG converter for a voltage of 24 V.The simulated graphical representation of inductors and diodes voltage and current are pictured in Figures 12 and 13.The performance of SI-VMHG converter is analyzed under different conditions, including voltage at the input, setpoint/reference voltage, and output/load power variations.
To investigate the controller's performance with the SI-VMHG converter topology, different voltage inputs are varied over a wide range of time intervals from 24 to 48 V.The input voltage of 24 V is initially considered at time t = 0 s.The output/load voltage and the load power are regulated to 200 V and 100 W, respectively.A voltage variation of 24-34 V occurred at t = 0.4 s.The change in input voltage tends to enhance the output voltage and load power.The error signal is generated and fed into the controller unit for generating the gating signal to maintain the output voltage and load power.Similarly, the source voltage varies from 34 to 48 V   at t = 0.7s; the controller senses the change in output voltage and generates the gating signal for maintaining the voltage at an output of 200 V.The pictorial representation of the input voltage at different time durations is displayed in Figure 14, and the values are tabulated in Table 3.
The controllability of the controller can be studied by altering the setpoint/ reference voltage.On the source side of the converter, the voltage of 24 V is maintained.During time t = 0 s, the setpoint/reference voltage is made at 200 V, and the output voltage and load power are maintained at 200 V and 100 W, respectively.At time t = 0.4 s, the setpoint value is increased from 200 to 220 V; the controller senses the change in voltage and generates the required gating signal to maintain the reference voltage.Likewise, during time t = 0.7 s, the reference voltage decreases from 220 to 180 V.At that time, the controller generates the PWM signal to maintain the reference voltage.The controller took less than 0.02s to maintain the reference value, the load/output power and is presented in Figure 15.The changes in voltage, current, and power values related to the setpoint/reference values variations are tabulated in Table 4.
The proposed converter is again tested under different load powers at different durations to assess its working with the controller.During t = 0 s, the converter is operated at half the rated load power of 50 W. Power and voltage are maintained at the output.The load power is increased from 50 to 100 W during time t = 0.5 s.The controller estimates the change in load power variations, and an appropriate gating signal is applied to the power MOSFET to turn on.The change in load power variations at different time durations is shown in Figure 16, and the corresponding variations in voltage, current and power values at the source side and load end are tabulated in Table 5.

Experimental prototype model
A hardware prototype model of the SI-VMHG topology isdeveloped to check the simulation results.Prototype hardware is designed using a voltageof 20 and 240 V at input and output for power at the load of 100 W. The detailed hardware specification of the SI-VMHG topology is tabulated in Table 6. Figure 17 presents the experimental prototype model of the proposed SI-VMHG topology.
The gating pulse for the converter is obtained using a PIC 18F452 microcontroller.The power circuit and the gate driver circuit are presented in Figure 17.In order to obtain a load voltage of 100 V from a source voltage of 10 V, a duty ratio of 0.5 is needed.The load voltage of 86 V is obtained experimentally and is shown in Figure 18(a).Likewise, for a 200 V load voltage, input voltage of 20 V, the experimental output voltage of 199 V is obtained and pictured in Figure 18(b).The inductors (L 1 , L 2 and L 3 ) current waveforms are obtained experimentally and displayed in Figure

Conclusion
The proposed SI-VMHG converter is based on a boost converter that uses switched inductors and voltage multipliers.The proposed topology maintains a continuous current at the source side, making power devices less susceptible to switching stress.The converter is modelled for the voltage rating of 24 V/200 V

Disclosure statement
No potential conflict of interest was reported by the author(s).

Mode 3 :
The power semiconductor switch S is in the ON position between time interval [t 2 -t 3 ].The D 2 and
18 W. Power Loss Due to Diode: The power loss associated with the diodes D 1 to D 8 is given in (37).Let, R D is 17

Figure 9 .
Figure 9. Generation of PWM signal using PI controller.

Figure 12 .
Figure 12.Closed-loop simulated current and voltage waveforms of inductors in proposed SI-VMHG converter.

Figure 13 .
Figure 13.Closed-loop simulated waveforms of inductor current and capacitor voltage of proposed converter.

Figure 14 .
Figure 14.Performance analysis of proposed SI-VMHG converter under input voltage variation.

Figure 15 .
Figure 15.Performance analysis of proposed SI-VMHG converter under setpoint/reference voltage variation.

Figure 16 .
Figure 16.Performance analysis of the proposed converter under load power variations.

Figure 18 .
Figure 18.(a) Gating pulse and output voltage waveforms for the input voltage of 10 V; (b) output voltage waveforms for the input voltage of 20 V; (c) gating pulse and inductor (L 1 and L 2 ) current waveforms; (d) gating pulse and inductor (L 3 ) current waveforms; (e) Diode D1 current and voltage waveforms; (f) Diode (D 2 and D 3 ) current and voltage waveforms; (g) Diode (D 4 ) current and voltage waveforms; (h) Diode (D 5 ) current and voltage waveforms; (i) Diode (D 6 ) current and voltage waveforms; (j) gating pulse and diode (D 7 ) voltage waveforms; (k) diode (D 8 ) current and voltage waveforms; (l) switch current and voltage waveforms; (m) step response for input voltage variation waveforms; and (n) step response for load power variation waveforms.

Table 1 .
Analysis of the SI-VMHG converter topology with previously designed converters.