High-performance programmable grounded resistor and its applications

ABSTRACT Programmable resistor and analog computational circuits are essential for many applications such as analog signal processing units, automatic gain control, neural, fuzzy and instrumentation systems. A high-performance programmable grounded resistor (PGR) using complementary metal oxide semiconductor (CMOS) technology is proposed in this paper. A highly linear CMOS resistor with equivalent resistance ranging from 9.4 to 1.5 kΩ is obtained by cancelling the non-linear term present in the current equation of an MOSFET working in the linear region. The proposed resistor operates on both positive as well as negative input voltage. The inherited features of PGR are simplicity, extensive control voltage range, wider bandwidth and low-power dissipation. Additionally, analog computational units such as multiplier, squarer and divider are also discussed as applications of the PGR. All circuits are implemented and simulated using TSMC 0.13 µm CMOS technology in SPICE.


Introduction
Resistor is one of the basic elements of analog signal processing applications [1,2]. Programmable resistors with accurate resistance value are imperative to on-chip-based systems and specific applications where variable resistance value is required. Unfortunately, the use of resistors has reduced in the field of integrated circuits due to the non-availability of accurate and programmable resistors. Many configurations have been proposed to implement programmable resistors using different techniques. Several resistors have been realized [3][4][5][6][7][8][9][10][11][12] using complementary metal oxide semiconductor (CMOS) technology and can be programmed externally. Few resistors are implemented using current conveyors, operational transconductance amplifier (OTA) arrays and the floating-gate metal oxide semiconductor transistor (FGMOS) technique. The drawbacks of these proposed resistors are short range of programmability, large silicon area and high power dissipation. Various applications of CMOS resistors are current to voltage converters, current mode dividers [12][13][14], multipliers [13,[15][16][17][19][20][21], filters [22][23][24] and automated measurement systems [25]. These analog computational blocks which are implemented using these reported resistors lack high performance.
A simple CMOS-based programmable grounded resistor (PGR) is proposed in this paper which is operating on minimal power of only 34.1 μW. The other salient characteristics of the presented block are broad control range, high linearity, wider bandwidth, less silicon area and ability to operate on both positive and neg-ative input voltage values which proves it to be the most appropriate for various signal processing applications. Three simple and programmable analog computational blocks based on PGR, namely analog amplitude modulator (using multiplier), squarer and voltage divider have been suggested. These proposed circuits are most appropriate for analog systems where accuracy and programmability are crucial.
The paper is organized as follows: the second section presents proposed PGR. Second-order effects are considered in the third section. An amplitude modulator and squarer are presented in the fourth section in addition to voltage mode divider. The fifth section validates the theoretical results from simulation outcomes to confirm the effectiveness of proposed circuits. Lastly, the paper is concluded in the sixth section.

Proposed PGR
The proposed PGR and its symbol are shown in Figures 1 and 2. It consists of two N-type metal oxide semiconductor (NMOS) transistors M 1 and M 2 , operating in linear region. V in and I in are the input voltage and current, respectively and V c is the control voltage to tune the resistance of the circuit.
According to the square law relation, the drain current of M 1 operating in the triode region is given by Equation (1).
(1)  This drain current is valid for the condition given in Equation (2) where k 1 is the transconductance parameter of M 1 .
The value of V c should be selected greater than the threshold voltage V tn1 for proper operation of circuit. The gate voltage applied to transistor M 2 is V in + V c and the corresponding drain current is According to Figure 2, the input current I in is summation of I 1 and I 2 Since the drain to source voltages of both transistors are equal and it is fair enough to assume that threshold voltages are the same, V tn1 = V tn2 = V tn in addition to the same transconductance parameters; k 1 = k 2 = k, the current expression is rewritten as Hence, input resistance can be given as It can be seen that the non-linear term of Equation (1) is cancelled by current I 2 , entailing the proposed circuit to behave as a linear resistor.  are biased to act as a current mirror. The drain currents of I 3 and I 4 are equal with assumption that transconductance parameters and threshold voltages of PMOS and NMOS transistors are equal respectively. Thus, gate to source voltages of M 3 and M 4 are also same and can be given as where V ss = −V c and V t3 = V t4 for the desired operation. Thus,

Second-order effects
It is necessary to consider second-order effects on the proposed circuits to analyse non-idealities [26].

Mobility degradation
The carrier's mobility decreases under high electric field circumstances and is given by the expression: The equivalent resistance equation will be modified by factor m and is expressed by k is µ0CoxW/L and m is 1/1 − θ (V in − V tn ) and the value mobility degradation parameter of θ ranges from 0.001 to 0.1 V −1 . The errors due to extremely small value of degradation parameter θ are insignificant. Thus, the output function will be slightly affected, except the voltage mode divider circuit which is independent of this factor.

Temperature variation
The relationship between the mobility of carriers and the temperature is given below: It is known that the temperature variation affects the transconductance parameter β. Mobility is calculated at T c to analyse the temperature variation where T is the absolute temperature (300 K). The value of constant parameter γ ranges from 1.5 to 2. The mobility decreases by maximum 6.3% (γ = 2) and minimum by 4.7% for γ = 1.5. The interconnect resistance of MOSFET also gets affected by temperature variations and is expressed as below: where R i is a resistance at temperature T i and the value of α is an empirical temperature coefficient of resistance with value 0.004 for copper wire and 0.0043 for aluminium wire. R 0 and T 0 are reference resistance and temperature, respectively. Suppose R 0 is 30 k at 20°C, the value of R i at 30°C is 30.12 k for copper and 30.129 k for aluminium after using Equation (12) and results in an increase of 4% and 4.3%, respectively. It can be seen that the variations in interconnect resistance and mobility due to temperature will almost nullify each other. Thus, proposed circuits are less prone to error due to temperature variations.

Mismatch effect
The mismatches in threshold voltages of transistors in the PGR circuit can add a DC offset to expression of equivalent resistance which can be nullified by offset applied externally. Second, the inequality of transconductance parameters can also cause deviation from the desired result. Assume that the k 1 is transconductance parameter of M 1 and k 1 + k 1 of M 2 of PGR. The current expression given in Equation (4) can be rewritten as follows: The value of k 1 is much smaller to affect the expression given in Equation (14) by a considerable amount. Moreover, a DC offset current added to circuit can nullify this mismatch.

Proposed analog multiplier and squarer
An analog voltage multiplier can be implemented using two proposed PGRs as depicted in Figure 4. The gate voltages of V G1a and V G2a are V c + V 2 , and V 1 + V c and input voltages for V G1b and V G2b are V c and V c − V 1 , respectively. This analog multiplier can be utilized to realize amplitude modulating function. After simplification using Equations (1)-(6), the currents I a and I b are as follows: Thus, I out is found to be I a + I b and is given by Hence, the above expression results in the multiplication of two input voltages with the assumption of matched transistors. Thus, it can be used to realize analog amplitude modulator. For squarer, if V 1 = V 2 = V in is chosen then the configuration shown in Figure 4 will function as a amplitude squarer with expression given below.
Bias voltages V 1 + V c , V 2 + V c and -V 1 + V c are generated using the bias circuit shown in Figure 3.

Proposed analog voltage divider
A new voltage mode divider is shown in Figure 5 and implemented using two PGRs and one NMOS transistor M 3 operating in the saturation region. Using Equations (1)-(6), the current I 1 can be given as The expression for I out is The output voltage V out can be obtained from Equations (19) and (20) and expressed as Thus, the function of voltage division is achieved which can be programmed by control voltage V c . Bias voltages V c + V th and V 2 + V th are obtained from the circuit mentioned in Figure 3 with V ss = −V th . V c + V 1 and V out + V 2 are achieved using the bias circuit shown in Figure 3 again when the source of the M 3 of Figure 3 is connected to V th instead of ground.

Simulation results and comparisons
All the circuits proposed in this paper are validated through simulations using T-Spice in 0.13 μm TSMC BSIM3, CMOS technology with level 49. The aspect ratios of all transistors are chosen to be 1:1. V dd and V ss vary as the value of V c varies from 0.5 to 1.5. Figure 6 shows I-V characteristics where the input current is applied to the circuit and corresponding voltage V in is measured for different values of control voltage V c .
The respective values of R eq are shown in Table 1. It can be seen that it is validating the analytical analysis that it functions as a linear resistor programmable by V c with equivalent values of resistance, R eq ranging from 9.46 k to 1.5 k . The effect of temperature on R eq is analysed and shown in Figure 7. R eq varies from 9.8 k to 9.0 k for temperature ranging from 50°C to −50°C leading to minor deviations.
In Figure 8, distortion analysis of PGR is measured for different values of sinusoidal input current of magnitude up to 50 μA at a frequency of 1 MHz. Maximum total harmonic distortion (THD) measured is 2.7% at I in = 50 μA. The power dissipation observed for the     circuit shown in Figure 2 is 946 nW which is remarkably low. The total power dissipation of PGR including bias circuit for V in + V c is 34.1 μW at V c = 1 V, which is again low. The frequency response of PGR for R eq = 9.4 K at V c = 0.5 V is shown in Figure 9 with constant magnitude of equivalent resistance up to 130 MHz. The transient analysis and fast Fourier transform characteristics of the proposed PGR is given in Figure 10 for current input signal of magnitude 45 μA at  frequency of 1 MHz. The value of R eq is set to approximately 2 k to get both the responses. The output of the summation circuit is also shown in Figure 11 to verify the implementation given in Figure  2. Figure 11 depicts the linear increase in the output, V in + V c when V in is varying and V c is constant at a value of 1 V. Table 2 compares the proposed PGR with existing resistors available in the literature. The presented CMOS resistor is linear due to cancellation of nonlinear terms of drain equations of both NMOS transistors. It works on positive as well as negative values of the input voltage V in (V in > 0 and V in < 0), whereas many reported resistor realizations operate only for positive values of V in . It is evident that the proposed PGR achieved wider bandwidth of 130 MHz and provides broad range of programmability using control voltage V c varying from 0.5 to 2.5 V. It also dissipates less power up to 34.1 μW when compared to the reported circuits. THD observed is 2.7% which also low. Thus, the proposed PGR is most suitable for high-performance analog applications demanding low-power dissipation, tunablility, linearity and less silicon area.
The operation of the analog amplitude modulator using the proposed voltage multiplier is analysed with input waveforms of V 1 (t) = 100 mV sin(2π × 10 5 ) and V 2 (t) = 200 mV sin(2π × 10 6 ) shown in Figure 12. The aspect ratio chosen for all transistors is 6.5 μm/ 0.13 μm. The modulated output waveform is depicted in Figure 13 for given input signal. For squarer function, Figure 14 depicts V 1 = V 2 = 100 mV sin(2π *10 6 ) and the output waveform is given in Figure 15 justifying the analytical analysis. The bandwidth measured is 79.9 MHz with a linear range of input voltage from +0.6 V to −0.6 V. The DC simulation results of the proposed voltage divider are shown in Figure 16 when V 1 is varied from 0 to 800 mV for different values of V 2 ranging from 0.6 to 1 V. The aspect ratio of all transistors chosen for the voltage mode divider circuit is 1:1 except M 3 which is 10:1. The bandwidth of the voltage divider is found to be 89 MHz and depicted in Figure 17.

Conclusion
This paper proposed a new high-performance PGR and its applications in analog arithmetic circuits such as analog amplitude modulator, squarer and voltage mode divider. The power dissipation of PGR measured is 34.1 μW which is quite low. Wider bandwidth and broad programmability range are achieved. All circuits exhibit simplicity while validating the claimed theoretical results from simulation results. These blocks are believed to be beneficial for low-power analog applications such as analog fuzzy hardware, artificial neural networks and automated measurement systems.