A floating-output interleaved boost DC–DC converter with high step-up gain

ABSTRACT A new interleaved boost converter with high step-up gain is presented in this paper. The proposed topology integrates coupled inductors and floating-output capacitors technique into interleaved boost converter to provide high step-up voltage gain without extreme duty cycle. The voltage stress on the power switches and diodes is very low, so low-cost and high-performance semiconductor devices can be employed. Also, the reverse recovery problem of all diodes is mitigated and zero-current-switching (ZCS) turn-on operation of the main switches is established as well. In addition, the passive clamp circuits are employed to suppress the voltage spikes across the main switches during turn-off instants. The operating principles and steady-state analysis of the proposed converter in continuous condition mode are explained. Finally, the simulation and experimental results of prototype 25–400 V circuit with 200 W output power are provided to verify the performance of presented topology.


Introduction
High step-up DC-DC converters are employed in numerous applications, such as renewable energy systems, motor drives, uninterruptible power systems and electric vehicles [1][2][3][4][5][6]. In these applications, a high step-up converter is required to adapt the low voltage level of batteries or photovoltaic cells to the high-voltage DC bus [7,8]. In order to perform this voltage conversion, various isolated DC-DC converters are presented in which high voltage gain can be achieved by increasing the transformer turns ratio [9,10]. Nevertheless, these converters suffer from high circulating currents, high voltage stress and low efficiency [11,12].
According to the recent studies, non-isolated DC-DC converters are favourable in high step-up application due to lower size, lower circuit cost and higher efficiency than the isolated types [13]. Conventional boost and buck-boost converters theoretically have a high voltage gain. However, due to many limitation factors, such as equivalent series resistance of the passive elements and reverse recovery problem of the output diode, a high step-up gain cannot be achieved in practice [14][15][16]. In order to reduce the switches voltage stress in high step-up applications, conventional three-level boost converter can be used. Also, the size of the input inductor is lower than the boost converter [17,18]. However, the voltage gain is still limited. Conventional cuk, sepic and zeta converters can be employed as a high step-up converter, but they are more complex than the boost converter [19,20]. Some efforts are made to combine sepic and boost converters. But despite using further elements, the voltage gain is limited [21,22].
Cascade technique is a simple approach to providing high voltage gain [23,24]. However, these converters need two individual magnetic cores, which increase circuit cost and complexity. Also, due to double power processing, the whole converter efficiency is low. Coupled inductors (CI)-based boost converters are widely used to improve the voltage gain, since the CI turns ratio provide a control freedom in addition to the duty cycle. Also, owing to the leakage inductance of coupled inductors the zero-current-switching (ZCS) turn-on operation of the main switch is accomplished and the reverse recovery problem of output diode is suppressed [25][26][27][28]. Despite single-phase CI converters advantages, the pulsating input current ripple reduces the input capacitor lifetime [29]. In order to reduce the input current ripple, interleaved boost converters with winding cross-coupled inductors (WCCI) are presented [30][31][32][33][34]. In these topologies, passive or active clamp circuits are employed to absorb the leakage inductor energy and provide soft switching operation. In [35][36][37], some interleaved boost converters with voltage multiplier cells are presented. Owing to using the WCCI technique and voltage multiplier cell, an extendable high step-up voltage gain is provided and the input current ripple is conspicuously low. Also, the automatic current sharing feature is established due to using series capacitors between the two interleaved phases. Some interleaved boost converters with series capacitors and voltage multiplier cells are presented CONTACT Ghazanfar Shahgholian shahgholian@iaun.ac.ir in [38,39], which have a voltage gain higher than the conventional interleaved boost converter. In [40], an interleaved boost converter with floating-output capacitors is introduced. In this topology, the input voltage source is connected in series with output capacitors to provide high voltage gain. Also, the diodes and switches voltage stress is lower than the conventional interleaved boost converter.
In this paper, a new interleaved boost converter is presented for high step-up applications. The proposed converter encompasses a high voltage gain without extreme duty cycle and low voltage stress across the semiconductor devices with the same number of MOSFET switches in comparison with the conventional interleaved boost converter. Also, the leakage inductor of the coupled inductors provides ZCS turn-on operation of the main switches and alleviates the reverse recovery problem of all diodes. Furthermore, the passive clamp circuits are used to absorb and recycle the leakage energy into the circuit, which leads to suppressing the voltage spikes across the main switches. Thus, low-voltage MOSFET switches with low ON-resistance can be employed to reduce the conduction losses. The remainder of this paper is arranged as follows. In Section 2, the operating principles of the proposed converter in continuous condition mode (CCM) are discussed in details. Steady-state analysis and features of the proposed converter are analysed in Section 3. Simulation and experimental results are presented in Section 4. This paper concludes with some final remarks in Section 5.

Proposed converter and operating principles
The circuit configuration of the proposed converter is shown in Figure 1. This converter is based on two CI boost converter modules, which are interleaved connected at the input and series connected at the output. The input gate signals of the converter switches have a 180-degrees phase shift which causes interleaved operation of two modules. In this topology, inductors L 1l and L 2l comprise the two coupled inductors. Switches S 1 and S 2 are the main switches and diodes D 1 and D 2 are the output-rectifying diodes of the boost converter. Diodes D C1 and D C2 along with capacitors C c1 and C c2 comprise two passive clamp circuits which recycle the leakage inductors energy and limit voltage stress on the main switches. In order to simplify the operating principles analysis of the proposed converter, some assumptions are made as follows: -All diodes and MOSFET switches are considered to be ideal. -All capacitors are large enough. Hence, their voltage ripple can be neglected. -The operating duty cycle of the main switches S 1 and S 2 is equal. -The coupled inductors are modelled as a magnetizing inductor, a leakage inductor and an ideal transformer with n = n 12 /n 11 = n 22 /n 21 turns ratio.
The typical waveforms of the proposed converter at steady-state condition are given in Figure 2. According to the following considerations, the proposed converter has eight operating modes during one complete switching cycle. Owing to the symmetrical operation of switches S 1 and S 2 , only four operating modes of switch S 1 are explained. The equivalent circuit of each mode is shown in Figure 3. Before t 0 , both switches S 1 and S 2 are ON and the magnetizing inductors L M1 and L M2 are charged through the input.
Mode 1 [t 0 ¡ t 1 ]: At t 0 , switch S 1 is turned off and clamp diode D C1 starts to conduct. During this mode, a part of magnetizing inductor current i LM transfers to the output via the secondary side of the coupled inductors and diode D 1 . Also, the leakage energy which stores in L lk1 is absorbed by the clamp capacitor C c1 . Therefore, the leakage inductor current i Llk1 decreases linearly.
At t 1 , i Llk1 reaches zero and this mode ends. During this interval, the equations of the leakage inductor and the magnetizing inductors currents are as follows: : At t 1 , the leakage inductor current becomes zero and the clamp diode D C1 is turned off without any reverse recovery problem. During this mode, the magnetizing inductor current i LM is charging the output capacitor C 1 through the secondary side of the coupled inductors. Thus, i LM is decreasing linearly as follows: Figure 1. Circuit diagram of the proposed converter.   Mode 3 [t 2 ¡ t 3 ]: At t 2 , switch S 1 is turned on. Owing to the leakage inductor L lk1 , switch S 1 is turned on under ZCS conditions. During this mode, the leakage inductor current i Llk1 is increasing linearly. At t 3 , the magnetizing inductor and the leakage inductor currents become equal and the diode D 1 is turned off with no reverse recovery problem. Following equations represent the leakage inductor and the diode D 1 currents in this interval: Mode 4 [t 3 ¡ t 4 ]: At t 3 , both switches S 1 and S 2 are ON and all rectifying diodes are OFF. The leakage and magnetizing inductors are charged via the input voltage source V in . Also, the capacitors C 1 and C 2 along with V in provide energy to the output load R L . During this mode, equations of the magnetizing and leakage inductors currents are expressed as follows: :.t À t 3 / (7)

Steady-state performance analysis of the proposed converter
To simplify the steady-state analysis, the mode 1 is neglected since the duration of this mode is very short.

Conversion ratio
Due to voltage-second balance for the inductors of all switching circuits, voltage-second balance can be written for inductors L m1 and L m2 which results in the following equation [41]: Also, in this circuit, due to large values of capacitors and for simplicity of voltage relationships, C 1 and C 2 are considered identical: According to the mode 3, the clamp capacitors C c1 and C c2 recycle the energy of leakage inductors. By applying the KVL principle, the voltages of C c1 and C c2 are determined as follows: By substituting (10) and (9) into (8), the voltage gain of the proposed converter is obtained as follows: Figure 4 shows a comparison between the proposed converter and some other similar interleaved DC-DC topologies in terms of voltage gain. To make a fair comparison, the coupled inductors turns ratio (n) is considered equal to 2. As can be observed, the proposed converter has a higher voltage gain than the conventional interleaved boost converter and the converters presented in [42,43]. The interleaved converter, which is presented in [44], has a higher voltage gain in duty cycles below 0.4. However, in duty cycles higher than 0.4, which is favourable in high step-up applications, the voltage gain of proposed converter goes out the voltage gain of [45]. Hence, the proposed converter is an appropriate topology for applications, where a high step-up conversion ratio is required.

Voltage stress on semiconductor devices
According to the foregoing analysis, the voltage stress on the main switches, clamp diodes and output diodes of the proposed converter is derived as follows: The normalized voltage stress graph of the semiconductor devices versus the coupled inductors turns ratio is plotted in Figure 5. It can be observed that the voltage stress on the main switches and clamp diodes is reduced as the coupled inductors turns ratio increases. On the other hand, the voltage stress on the output diodes is increased. Therefore, the coupled inductors turns ratio should be designed properly to minimize the voltage stress on the main switches and diodes.

Passive elements design
Regarding the desired current ripple on the magnetizing inductors ΔI Lm in CCM operation, the values of L M1 and L M2 are calculated as follows: The leakage inductor of the coupled inductors causes ZCS turn-on of the main switches S 1 and S 2 . Hence, to accomplish the ZCS condition for the main switches, the value of the leakage inductors L lk1 and L lk2 is obtained as follows: where t r is the current rise time of the MOSFET switches and ΔI s denotes the current variation amplitude of the switches during turn-on instant. The desired voltage ripple (ΔV c ) is the main criteria for choosing the value of the output capacitors. Hence, the proper value of converter capacitors is obtained as follows: The values of clamp capacitors C c1 and C c2 are selected such that half of the resonant period formed between C c and L lk should be greater than the turn-off period of the main switches:

Simulation and experimental results
A prototype circuit of the proposed converter is built to evaluate the performance of the proposed topology. The photograph of the implemented circuit is shown in Figure 6. The prototype circuit is designed to convert 25 V input to 400 V output at 200 W nominal power and 100 kHz switching frequency. Specifications of the prototype circuit are given in Table 1. Moreover, the proposed converter is simulated by ORCAD-PSpice simulator. The simulation circuit is shown in Figure 7. In the simulation circuit, an   accurate PSPICE model of all semiconductor devices is used. Also, the coupling coefficient of the coupled inductors is selected 0.98 and the operating duty cycle is 0.7. Figures 8 and 9 show the simulation and experimental waveforms of the proposed converter, respectively. It can be seen that the experimental results show a good agreement with simulation results. The voltage and current waveforms of the main switch S 1 and S 2 are illustrated in Figures 8(a) and 9(a). It can be seen from figures that, for 400 V output voltage, the voltage stress on the MOSFET switches is below 100 V, which is lower than 25% of the output voltage. In addition, the leakage inductors have accomplished the ZCS turn-on operation of main switches as well. Figures 8(b) and 9(b) represent the voltage and current waveforms of the clamp diodes D c1 and D c2 . As can be seen, the voltage stress of clamp diodes is the same as the main switches. Also, the reverse recovery problem of these diodes is completely alleviated. The simulation and experimental waveforms of the output diodes D 1 and D 2 are shown in Figures 8(c) and 9(c).
The voltage stress on the output diodes, which are the most stressful devices in high step-up DC-DC converters, is about 200 V, which is half the output voltage. Also, the reverse recovery problem of the output diodes is completely eliminated.
The efficiency diagram of the proposed converter under different output load condition is plotted in Figure 10. As can be observed, the maximum efficiency of the proposed converter is 94.5% at 140 W output power, and the full-load efficiency is 94.1%.

Conclusion
In this paper, a new interleaved high step-up DC-DC converter based on the floating-output capacitors technique was introduced. The steadystate analysis and derived equations represent that the voltage gain of the proposed converter is much higher than the conventional interleaved boost converter. In this topology, the voltage stress on the main switches and diodes is very low. Consequently, low-voltage, high-performance MOSFET switches and scotty diodes can be used. Also, the output and clamp diodes turn off under ZCS condition.
Moreover, the leakage inductors energy is recycled into the circuit, so the voltage spikes across the main switches are avoided. At last, the proposed converter was simulated and a 200 W prototype circuit was implemented to prove the validity of the steady-state analysis.